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[198.145.21.10]) by mx.google.com with ESMTPS id j91-v6si1171374pld.402.2018.07.20.01.04.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 20 Jul 2018 01:04:51 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=OEEx19lA; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 84B9D20D7ADC3; Fri, 20 Jul 2018 01:04:51 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::544; helo=mail-pg1-x544.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pg1-x544.google.com (mail-pg1-x544.google.com [IPv6:2607:f8b0:4864:20::544]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 7EB5A2098EAB9 for ; Fri, 20 Jul 2018 01:04:50 -0700 (PDT) Received: by mail-pg1-x544.google.com with SMTP id p23-v6so6177399pgv.13 for ; Fri, 20 Jul 2018 01:04:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=RdSQ6jFwLbLUW7Y0utDwChKzUVWFUVOazC9FNcqya9U=; b=OEEx19lAzIYkq5y/b9A5O3d35zCYCyEgsvn9ax0vN0wAHKRyX0Nh7BuAFwP56e8Np7 GuR6e38s/Ymzupi41I1lghjbx15SBkEFLwXTNjPR7KM0jgysxCdigIYxUwCridmGiD1T Rtvs4B5HZ8W+QO18yLX1Jl3FWSCKsvPQ9qLqI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=RdSQ6jFwLbLUW7Y0utDwChKzUVWFUVOazC9FNcqya9U=; b=hcXj5/YqwsP8HudVDElIJIz4OSAM+uGP4qI4SgZqhGErCUUbjmWfAP/7CQRyFAvNWw AG4Yd8u4QdcFqowlIilH1YzlaMPefSteXmN4a0OS0tSGlh2pdW+yICy+Mf3II5mmwtBE O08JWt/tc58QsSkFOMNfmI3/roqOtoUoUBBQnFIw/jpkEyjq1qTbCd3P5PKYdf6GaIuf gi2wSul9s6xno8hhgiayVt65Mj/VuTQc5QdFfX2Zf2CRI5PmGze85OiQYZLlLeFma5vX VNhP101DtHSknA5EaVImXJaPqZbRAmJgFsQUk+Ac5yEO5nnkRNJcwbd2evskhqMXc75J 2Jng== X-Gm-Message-State: AOUpUlGYliMo2TscMHxxOec206CzM0/BgWyBJ0wpFdFepuxlDGv1DsEc YD/lSj30F/kB9tpX1CWliM81x1XqrbU= X-Received: by 2002:a62:404e:: with SMTP id n75-v6mr1150014pfa.232.1532073890183; Fri, 20 Jul 2018 01:04:50 -0700 (PDT) Received: from localhost.localdomain ([120.31.149.194]) by smtp.gmail.com with ESMTPSA id n18-v6sm2066812pfa.50.2018.07.20.01.04.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 20 Jul 2018 01:04:49 -0700 (PDT) From: Ming Huang To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Fri, 20 Jul 2018 16:02:35 +0800 Message-Id: <20180720080242.3777-7-ming.huang@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180720080242.3777-1-ming.huang@linaro.org> References: <20180720080242.3777-1-ming.huang@linaro.org> Subject: [edk2] [PATCH edk2-platforms v1 06/13] Hisilicon/Pci: move EnlargeAtuConfig0() to PciPlatformLib X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, john.garry@huawei.com, zhangjinsong2@huawei.com, Michael D Kinney , huangdaode@hisilicon.com, guoheyi@huawei.com, wanghuiqiang@huawei.com MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" we move all platform specific code to platform specific module, not in PciHostBridge driver. This is to prepare for switching to generic PciHostBridge driver, so This patch is to move EnlargeAtuConfig0() into PcieInitDxe, in PlatformNotify() of EFI_PCI_PLATFORM_PROTOCOL and implement api PhaseNotifyPlatform for PciPlatform driver. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Heyi Guo Signed-off-by: Ming Huang Cc: Ard Biesheuvel Cc: Leif Lindholm Cc: Michael D Kinney --- Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c | 1 - Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h | 8 - Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c | 78 -------- Silicon/Hisilicon/Hi1610/Library/Hi161xPciPlatformLib/Hi161xPciPlatformLib.c | 199 ++++++++++++++++++++ 4 files changed, 199 insertions(+), 87 deletions(-) -- 2.17.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c index 9fa3f84098..e3d3988a64 100644 --- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c +++ b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c @@ -839,7 +839,6 @@ NotifyPhase( case EfiPciHostBridgeEndEnumeration: PCIE_DEBUG("Case EfiPciHostBridgeEndEnumeration\n"); - EnlargeAtuConfig0 (This); break; case EfiPciHostBridgeBeginBusAllocation: diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h index c04361fcee..435385491a 100644 --- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h +++ b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h @@ -401,10 +401,6 @@ PreprocessController ( #define EFI_RESOURCE_NONEXISTENT 0xFFFFFFFFFFFFFFFFULL #define EFI_RESOURCE_LESS 0xFFFFFFFFFFFFFFFEULL -#define INVALID_CAPABILITY_00 0x00 -#define INVALID_CAPABILITY_FF 0xFF -#define PCI_CAPABILITY_POINTER_MASK 0xFC - // // Driver Instance Data Prototypes // @@ -521,8 +517,4 @@ RootBridgeConstructor ( IN UINT32 Seg ); -VOID -EnlargeAtuConfig0 ( - IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This - ); #endif diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c index 273a322ee4..3c265ea433 100644 --- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c +++ b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c @@ -2218,81 +2218,3 @@ RootBridgeIoConfiguration ( return EFI_SUCCESS; } -BOOLEAN -PcieCheckAriFwdEn ( - UINTN PciBaseAddr - ) -{ - UINT8 PciPrimaryStatus; - UINT8 CapabilityOffset; - UINT8 CapId; - UINT8 TempData; - - PciPrimaryStatus = MmioRead16 (PciBaseAddr + PCI_PRIMARY_STATUS_OFFSET); - - if (PciPrimaryStatus & EFI_PCI_STATUS_CAPABILITY) { - CapabilityOffset = MmioRead8 (PciBaseAddr + PCI_CAPBILITY_POINTER_OFFSET); - CapabilityOffset &= PCI_CAPABILITY_POINTER_MASK; - - while ((CapabilityOffset != INVALID_CAPABILITY_00) && (CapabilityOffset != INVALID_CAPABILITY_FF)) { - CapId = MmioRead8 (PciBaseAddr + CapabilityOffset); - if (CapId == EFI_PCI_CAPABILITY_ID_PCIEXP) { - break; - } - CapabilityOffset = MmioRead8 (PciBaseAddr + CapabilityOffset + 1); - CapabilityOffset &= PCI_CAPABILITY_POINTER_MASK; - } - } else { - PCIE_DEBUG ("[%a:%d] - No PCIE Capability.\n", __FUNCTION__, __LINE__); - return FALSE; - } - - if ((CapabilityOffset == INVALID_CAPABILITY_FF) || (CapabilityOffset == INVALID_CAPABILITY_00)) { - PCIE_DEBUG ("[%a:%d] - No PCIE Capability.\n", __FUNCTION__, __LINE__); - return FALSE; - } - - TempData = MmioRead16 (PciBaseAddr + CapabilityOffset + - EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET); - TempData &= EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING; - - if (TempData == EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING) { - return TRUE; - } else { - return FALSE; - } -} - -VOID -EnlargeAtuConfig0 ( - IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This - ) -{ - UINTN RbPciBase; - UINT64 MemLimit; - LIST_ENTRY *List; - PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance; - PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance; - - PCIE_DEBUG ("In Enlarge RP iatu Config 0.\n"); - - HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This); - List = HostBridgeInstance->Head.ForwardLink; - - while (List != &HostBridgeInstance->Head) { - PCIE_DEBUG ("HostBridge has data.\n"); - RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List); - - RbPciBase = RootBridgeInstance->RbPciBar; - - // Those ARI FWD Enable Root Bridge, need enlarge iatu window. - if (PcieCheckAriFwdEn (RbPciBase)) { - MemLimit = GetPcieCfgAddress (RootBridgeInstance->Ecam, - RootBridgeInstance->BusBase + 2, 0, 0, 0) - - 1; - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, 1); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32) MemLimit); - } - List = List->ForwardLink; - } -} diff --git a/Silicon/Hisilicon/Hi1610/Library/Hi161xPciPlatformLib/Hi161xPciPlatformLib.c b/Silicon/Hisilicon/Hi1610/Library/Hi161xPciPlatformLib/Hi161xPciPlatformLib.c index de26259778..dad848e714 100644 --- a/Silicon/Hisilicon/Hi1610/Library/Hi161xPciPlatformLib/Hi161xPciPlatformLib.c +++ b/Silicon/Hisilicon/Hi1610/Library/Hi161xPciPlatformLib/Hi161xPciPlatformLib.c @@ -14,6 +14,7 @@ **/ #include +#include #include #include #include @@ -21,8 +22,14 @@ #include #include #include +#include +#include +#include #include +#define INVALID_CAPABILITY_00 0x00 +#define INVALID_CAPABILITY_FF 0xFF +#define PCI_CAPABILITY_POINTER_MASK 0xFC STATIC UINT64 @@ -37,6 +44,53 @@ GetPcieCfgAddress ( return Ecam + PCI_EXPRESS_LIB_ADDRESS (Bus, Device, Function, Reg); } +STATIC +PCI_ROOT_BRIDGE_RESOURCE_APPETURE * +GetAppetureByRootBridgeIo ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *RootBridge + ) +{ + EFI_STATUS Status; + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Configuration = NULL; + UINTN Hb; + UINTN Rb; + + Status = RootBridge->Configuration ( + RootBridge, + (VOID **)&Configuration + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "[%a:%d] RootBridgeIo->Configuration failed %r\n", + __FUNCTION__, __LINE__, Status)); + return NULL; + }; + + while (Configuration->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) { + if (Configuration->ResType == ACPI_ADDRESS_SPACE_TYPE_BUS) { + break; + } + Configuration++; + } + + if (Configuration->Desc != ACPI_ADDRESS_SPACE_DESCRIPTOR) { + DEBUG ((DEBUG_ERROR, "[%a:%d] Can't find bus descriptor\n", __FUNCTION__, __LINE__)); + return NULL; + } + + for (Hb = 0; Hb < PCIE_MAX_HOSTBRIDGE; Hb++) { + for (Rb = 0; Rb < PCIE_MAX_ROOTBRIDGE; Rb++) { + if (RootBridge->SegmentNumber == mResAppeture[Hb][Rb].Segment && + Configuration->AddrRangeMin >= mResAppeture[Hb][Rb].BusBase && + Configuration->AddrRangeMax <= mResAppeture[Hb][Rb].BusLimit) { + return &mResAppeture[Hb][Rb]; + } + } + } + + DEBUG ((DEBUG_ERROR, "[%a:%d] Can't find PCI appeture\n", __FUNCTION__, __LINE__)); + return NULL; +} + STATIC VOID SetAtuConfig0RW ( @@ -183,3 +237,148 @@ PciInitPlatform ( return; } +STATIC +BOOLEAN +PcieCheckAriFwdEn ( + UINTN PciBaseAddr + ) +{ + UINT8 PciPrimaryStatus; + UINT8 CapabilityOffset; + UINT8 CapId; + UINT8 TempData; + + PciPrimaryStatus = MmioRead16 (PciBaseAddr + PCI_PRIMARY_STATUS_OFFSET); + + if (PciPrimaryStatus & EFI_PCI_STATUS_CAPABILITY) { + CapabilityOffset = MmioRead8 (PciBaseAddr + PCI_CAPBILITY_POINTER_OFFSET); + CapabilityOffset &= PCI_CAPABILITY_POINTER_MASK; + + while ((CapabilityOffset != INVALID_CAPABILITY_00) && (CapabilityOffset != INVALID_CAPABILITY_FF)) { + CapId = MmioRead8 (PciBaseAddr + CapabilityOffset); + if (CapId == EFI_PCI_CAPABILITY_ID_PCIEXP) { + break; + } + CapabilityOffset = MmioRead8 (PciBaseAddr + CapabilityOffset + 1); + CapabilityOffset &= PCI_CAPABILITY_POINTER_MASK; + } + } else { + return FALSE; + } + + if ((CapabilityOffset == INVALID_CAPABILITY_FF) || (CapabilityOffset == INVALID_CAPABILITY_00)) { + return FALSE; + } + + TempData = MmioRead16 (PciBaseAddr + CapabilityOffset + + EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET); + TempData &= EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING; + + if (TempData == EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING) { + return TRUE; + } else { + return FALSE; + } +} + +VOID +EnlargeAtuConfig0 ( + IN EFI_HANDLE HostBridge + ) +{ + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *ResAlloc = NULL; + EFI_STATUS Status; + EFI_HANDLE RootBridgeHandle = NULL; + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *RootBridgeIo = NULL; + PCI_ROOT_BRIDGE_RESOURCE_APPETURE *Appeture; + UINTN RbPciBase; + UINT64 MemLimit; + + DEBUG ((DEBUG_INFO, "In Enlarge RP iATU Config 0.\n")); + + Status = gBS->HandleProtocol ( + HostBridge, + &gEfiPciHostBridgeResourceAllocationProtocolGuid, + (VOID **)&ResAlloc + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "[%a:%d] - HandleProtocol failed %r\n", __FUNCTION__, + __LINE__, Status)); + return; + } + + while (TRUE) { + Status = ResAlloc->GetNextRootBridge ( + ResAlloc, + &RootBridgeHandle + ); + if (EFI_ERROR (Status)) { + break; + } + Status = gBS->HandleProtocol ( + RootBridgeHandle, + &gEfiPciRootBridgeIoProtocolGuid, + (VOID **)&RootBridgeIo + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "[%a:%d] - HandleProtocol failed %r\n", __FUNCTION__, __LINE__, Status)); + // This should never happen so that it is a fatal error and we don't try + // to continue + break; + } + + Appeture = GetAppetureByRootBridgeIo (RootBridgeIo); + if (Appeture == NULL) { + DEBUG ((DEBUG_ERROR, "[%a:%d] Get appeture failed\n", __FUNCTION__, + __LINE__)); + continue; + } + + RbPciBase = Appeture->RbPciBar; + // Those ARI FWD Enable Root Bridge, need enlarge iATU window. + if (PcieCheckAriFwdEn (RbPciBase)) { + MemLimit = GetPcieCfgAddress (Appeture->Ecam, Appeture->BusBase + 2, 0, 0, 0) - 1; + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, 1); + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32) MemLimit); + } + } +} + +/*++ + +Routine Description: + + Perform Platform initialization by the phase indicated. + +Arguments: + + HostBridge - The associated PCI host bridge handle. + Phase - The phase of the PCI controller enumeration. + ChipsetPhase - Defines the execution phase of the PCI chipset driver. + +Returns: + +--*/ +VOID +EFIAPI +PhaseNotifyPlatform ( + IN EFI_HANDLE HostBridge, + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase, + IN EFI_PCI_CHIPSET_EXECUTION_PHASE ChipsetPhase + ) +{ + switch (Phase) { + case EfiPciHostBridgeEndEnumeration: + // Only do once + if (ChipsetPhase == ChipsetEntry) { + DEBUG ((DEBUG_INFO, "PCI end enumeration platform hook\n")); + EnlargeAtuConfig0 (HostBridge); + } + break; + default: + break; + } + + return ; +} +