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[198.145.21.10]) by mx.google.com with ESMTPS id e2-v6si2864241pgl.4.2018.07.04.00.51.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 04 Jul 2018 00:51:37 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=dlXJ9IHm; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 21481210D43BC; Wed, 4 Jul 2018 00:51:37 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c01::242; helo=mail-pl0-x242.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pl0-x242.google.com (mail-pl0-x242.google.com [IPv6:2607:f8b0:400e:c01::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 09598210C0F74 for ; Wed, 4 Jul 2018 00:51:36 -0700 (PDT) Received: by mail-pl0-x242.google.com with SMTP id z9-v6so2292834plo.1 for ; Wed, 04 Jul 2018 00:51:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=buApLzbytp/eU+y5SkiUgXplzV/QuA5DH7Tx2BdUVg4=; b=dlXJ9IHmfN0bZMFr+11g5HLUJlLmeKdDAD7W3wg9GbxMZnE0l+wvcKn9C1JWRtz57n QoNhJklY/i6ULLl8u4LZudQr52ccBhAuKiLanNB5giM1p0WzZNouXMhkqIKIx0LUnSnm TVTyPUMErDGu/wWHWCwT3d8Kd7iAs4cKvKkMQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=buApLzbytp/eU+y5SkiUgXplzV/QuA5DH7Tx2BdUVg4=; b=HvN32s/8671WyplK1nvY+xjqKuRnXQArTJZ90D26nQ4XbEI7+LMsa9hCpFvr6n3q2s +rjideNktT28SorHAdWJlRTb7qc3QWUP2SUsZWeOg1iDjwVMe0fxeoyzQIFJwHg0dfq2 xlV5gsaW7wyBGLdh+9SRiKNn2vmypXuFb56stCO7LDTdBRy4I3AxlMXmaaNkJkEE4/so /ihzKreG/XgaphIYbSaGcnYpNXQs4LvBJNX42bJGoDMTGpDJyxi4FkPLffqL7vUXdpgv 8TilDzqAULDnroktDN3DtpECoDKTcf0NexG20vLIZ0QsEyVuZ7LOPsXjkBL/8igARhWe IPSQ== X-Gm-Message-State: APt69E0WUsi/tSBbT0/G00DEYRS3Zepx4f4awSRYUBX5jVWZRGE2iWD1 PLXWfv2EEDFoAMExGL3YNyH5hg== X-Received: by 2002:a17:902:3f81:: with SMTP id a1-v6mr1043784pld.29.1530690695815; Wed, 04 Jul 2018 00:51:35 -0700 (PDT) Received: from localhost.localdomain ([120.31.149.194]) by smtp.gmail.com with ESMTPSA id d9-v6sm4803219pge.68.2018.07.04.00.51.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 04 Jul 2018 00:51:35 -0700 (PDT) From: Ming Huang To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Wed, 4 Jul 2018 15:51:14 +0800 Message-Id: <20180704075117.7427-4-ming.huang@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180704075117.7427-1-ming.huang@linaro.org> References: <20180704075117.7427-1-ming.huang@linaro.org> Subject: [edk2] [PATCH edk2-platforms v2 3/6] Hisilicon/D0x: Fix SetAtuConfig1RW bug X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, john.garry@huawei.com, zhangjinsong2@huawei.com, huangdaode@hisilicon.com, guoheyi@huawei.com, wanghuiqiang@huawei.com MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" The MemLimit is wrong when the Private->BusLimit equal 0xFF. This patch fix enumerating device plug in switch cart failed issue. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang Signed-off-by: Heyi Guo --- Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.17.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c index e5f66eaa4a..3f894e8eec 100644 --- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c +++ b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c @@ -666,7 +666,7 @@ void SetAtuConfig1RW ( ) { UINTN RbPciBase = Private->RbPciBar; - UINT64 MemLimit = GetPcieCfgAddress (Private->Ecam, Private->BusLimit + 1, 0, 0, 0) - 1; + UINT64 MemLimit = GetPcieCfgAddress (Private->Ecam, Private->BusLimit, 0x1F, 0x07, 0xFFF); UINT64 Cfg1Base = GetPcieCfgAddress (Private->Ecam, Private->BusBase + 2, 0, 0, 0); MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index);