| Message ID | 20180627070443.42886-6-ming.huang@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Improve D0x platforms and bug fix | expand |
On 27 June 2018 at 09:04, Ming Huang <ming.huang@linaro.org> wrote: > Optimize pcie space for promoting usage rate.Change regions order > of NA-Pcie2 and NB-Pcie1 to MEM-ECAM-IO in DAW,so MemoryRegion > can satisfy the requirement of larger address alignment. > OK, so I suppose it is the ECAM shift mode that is forcing you to change the bus ranges if you move the config space around, no? > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ming Huang <ming.huang@linaro.org> > Signed-off-by: Heyi Guo <heyi.guo@linaro.org> > --- > Platform/Hisilicon/D05/D05.dsc | 12 ++++---- > Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c | 8 ++--- > Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl | 8 ++--- > Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc | 8 ++--- > Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl | 32 ++++++++++---------- > 5 files changed, 34 insertions(+), 34 deletions(-) > > diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc > index 0e6d5912a0..ab7c5caf86 100644 > --- a/Platform/Hisilicon/D05/D05.dsc > +++ b/Platform/Hisilicon/D05/D05.dsc > @@ -305,13 +305,13 @@ > gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize|0xbf0000 > gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress|0xa9400000 > gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize|0xbf0000 > - gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress|0xa8800000 > + gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress|0xa8000000 > gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize|0x77f0000 > gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionBaseAddress|0xab400000 > gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize|0xbf0000 > gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionBaseAddress|0xa9000000 > gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize|0x2ff0000 > - gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress|0xb0800000 > + gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress|0xb0000000 > gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize|0x77f0000 > gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionBaseAddress|0xac900000 > gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize|0x36f0000 > @@ -336,10 +336,10 @@ > > gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase|0xA8400000 > gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase|0xA9400000 > - gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase|0xA8800000 > + gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase|0xA8000000 > gHisiTokenSpaceGuid.PcdHb0Rb3CpuMemRegionBase|0xAB400000 > gHisiTokenSpaceGuid.PcdHb0Rb4CpuMemRegionBase|0x8A9000000 > - gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase|0x8B0800000 > + gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase|0x8B0000000 > gHisiTokenSpaceGuid.PcdHb0Rb6CpuMemRegionBase|0x8AC900000 > gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase|0x8B9800000 > gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase|0x400A8400000 > @@ -353,10 +353,10 @@ > > gHisiTokenSpaceGuid.PcdHb0Rb0CpuIoRegionBase|0xa8ff0000 > gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase|0xa9ff0000 > - gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase|0xafff0000 > + gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase|0xaf7f0000 > gHisiTokenSpaceGuid.PcdHb0Rb3CpuIoRegionBase|0xabff0000 > gHisiTokenSpaceGuid.PcdHb0Rb4CpuIoRegionBase|0x8abff0000 > - gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase|0x8b7ff0000 > + gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase|0x8b77f0000 > gHisiTokenSpaceGuid.PcdHb0Rb6CpuIoRegionBase|0x8afff0000 > gHisiTokenSpaceGuid.PcdHb0Rb7CpuIoRegionBase|0x8bfff0000 > gHisiTokenSpaceGuid.PcdHb1Rb0CpuIoRegionBase|0x400a8ff0000 > diff --git a/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c b/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c > index 57283a1053..ed6c4ac321 100644 > --- a/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c > +++ b/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c > @@ -60,8 +60,8 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO > /* Port 2 */ > { > PCI_HB0RB2_ECAM_BASE, > - 0x80, //BusBase > - 0x87, //BusLimit > + 0xF8, //BusBase > + 0xFF, //BusLimit > PCI_HB0RB2_CPUMEMREGIONBASE ,//MemBase > PCI_HB0RB2_CPUMEMREGIONBASE + PCI_HB0RB2_PCIREGION_SIZE - 1, //MemLimit > (PCI_HB0RB2_IO_BASE), //IOBase > @@ -106,8 +106,8 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO > /* Port 5 */ > { > PCI_HB0RB5_ECAM_BASE,//ecam > - 0x0, //BusBase > - 0x7, //BusLimit > + 0x78, //BusBase > + 0x7F, //BusLimit > PCI_HB0RB5_CPUMEMREGIONBASE, //Membase > PCI_HB0RB5_CPUMEMREGIONBASE + PCI_HB0RB5_PCIREGION_SIZE - 1, //MemLimit > (PCI_HB0RB5_IO_BASE), //IoBase > diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl b/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl > index 50ccac1b06..9955f6dbeb 100644 > --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl > +++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl > @@ -412,9 +412,9 @@ > [0004] ATS Attribute : 00000000 > [0004] PCI Segment Number : 00000002 > > -[0004] Input base : 00008000 > +[0004] Input base : 0000f800 > [0004] ID Count : 00000800 > -[0004] Output Base : 00008000 > +[0004] Output Base : 0000f800 > [0004] Output Reference : 00000064 > [0004] Flags (decoded below) : 00000000 > Single Mapping : 0 > @@ -469,9 +469,9 @@ > [0004] ATS Attribute : 00000000 > [0004] PCI Segment Number : 00000005 > > -[0004] Input base : 00000000 > +[0004] Input base : 00007800 > [0004] ID Count : 00000800 > -[0004] Output Base : 00000000 > +[0004] Output Base : 00007800 > [0004] Output Reference : 0000007c > [0004] Flags (decoded below) : 00000000 > Single Mapping : 0 > diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc b/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc > index b47cfec7bd..64807b1714 100644 > --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc > +++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc > @@ -57,8 +57,8 @@ EFI_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE Mcfg= > { > 0xa0000000, //Base Address > 0x2, //Segment Group Number > - 0x80, //Start Bus Number > - 0x87, //End Bus Number > + 0xF8, //Start Bus Number > + 0xFF, //End Bus Number > 0x00000000, //Reserved > }, > //1p NB PCIe0 > @@ -73,8 +73,8 @@ EFI_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE Mcfg= > { > 0x8b0000000, //Base Address > 0x5, //Segment Group Number > - 0x0, //Start Bus Number > - 0x7, //End Bus Number > + 0x78, //Start Bus Number > + 0x7F, //End Bus Number > 0x00000000, //Reserved > }, > //1p NB PCIe2 > diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl > index 122e4f072c..3f09e5e568 100644 > --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl > +++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl > @@ -89,15 +89,15 @@ Scope(_SB) > Name (_HID, "PNP0A08") // PCI Express Root Bridge > Name (_CID, "PNP0A03") // Compatible PCI Root Bridge > Name(_SEG, 2) // Segment of this Root complex > - Name(_BBN, 0x80) // Base Bus Number > + Name(_BBN, 0xF8) // Base Bus Number > Name(_CCA, 1) > Method (_CRS, 0, Serialized) { // Root complex resources > Name (RBUF, ResourceTemplate () { > WordBusNumber ( // Bus numbers assigned to this root > ResourceProducer, MinFixed, MaxFixed, PosDecode, > 0, // AddressGranularity > - 0x80, // AddressMinimum - Minimum Bus Number > - 0x87, // AddressMaximum - Maximum Bus Number > + 0xF8, // AddressMinimum - Minimum Bus Number > + 0xFF, // AddressMaximum - Maximum Bus Number > 0, // AddressTranslation - Set to 0 > 0x8 // RangeLength - Number of Busses > ) > @@ -109,8 +109,8 @@ Scope(_SB) > Cacheable, > ReadWrite, > 0x0, // Granularity > - 0xa8800000, // Min Base Address > - 0xaffeffff, // Max Base Address > + 0xa8000000, // Min Base Address > + 0xaf7effff, // Max Base Address > 0x0, // Translate > 0x77f0000 // Length > ) > @@ -123,7 +123,7 @@ Scope(_SB) > 0x0, // Granularity > 0x0, // Min Base Address > 0xffff, // Max Base Address > - 0xafff0000, // Translate > + 0xaf7f0000, // Translate > 0x10000 // Length > ) > }) // Name(RBUF) > @@ -165,7 +165,7 @@ Scope(_SB) > { > Name (_HID, "PNP0C02") // Motherboard reserved resource > Name (_CRS, ResourceTemplate (){ > - Memory32Fixed (ReadWrite, 0xa8000000 , 0x800000) //ECAM space for [bus 80-87] > + Memory32Fixed (ReadWrite, 0xaf800000 , 0x800000) //ECAM space for [bus f8-ff] > }) > Method (_STA, 0x0, NotSerialized) > { > @@ -280,15 +280,15 @@ Scope(_SB) > Name (_HID, "PNP0A08") // PCI Express Root Bridge > Name (_CID, "PNP0A03") // Compatible PCI Root Bridge > Name(_SEG, 5) // Segment of this Root complex > - Name(_BBN, 0x0) // Base Bus Number > + Name(_BBN, 0x78) // Base Bus Number > Name(_CCA, 1) > Method (_CRS, 0, Serialized) { // Root complex resources > Name (RBUF, ResourceTemplate () { > WordBusNumber ( // Bus numbers assigned to this root > ResourceProducer, MinFixed, MaxFixed, PosDecode, > 0, // AddressGranularity > - 0x0, // AddressMinimum - Minimum Bus Number > - 0x7, // AddressMaximum - Maximum Bus Number > + 0x78, // AddressMinimum - Minimum Bus Number > + 0x7f, // AddressMaximum - Maximum Bus Number > 0, // AddressTranslation - Set to 0 > 0x8 // RangeLength - Number of Busses > ) > @@ -300,8 +300,8 @@ Scope(_SB) > Cacheable, > ReadWrite, > 0x0, // Granularity > - 0xb0800000, // Min Base Address > - 0xb7feffff, // Max Base Address > + 0xb0000000, // Min Base Address > + 0xb77effff, // Max Base Address > 0x800000000, // Translate > 0x77f0000 // Length > ) > @@ -314,7 +314,7 @@ Scope(_SB) > 0x0, // Granularity > 0x0, // Min Base Address > 0xffff, // Max Base Address > - 0x8b7ff0000, // Translate > + 0x8b77f0000, // Translate > 0x10000 // Length > ) > }) // Name(RBUF) > @@ -593,7 +593,7 @@ Scope(_SB) > 0x0, // Translate > 0x800000 // Length > ) > - QwordMemory ( //ECAM space for [bus 0-7] > + QwordMemory ( //ECAM space for [bus 78-7f] > ResourceConsumer, > PosDecode, > MinFixed, > @@ -601,8 +601,8 @@ Scope(_SB) > NonCacheable, > ReadWrite, > 0x0, // Granularity > - 0x8b0000000, // Min Base Address > - 0x8b07fffff, // Max Base Address > + 0x8b7800000, // Min Base Address > + 0x8b7ffffff, // Max Base Address > 0x0, // Translate > 0x800000 // Length > ) > -- > 2.17.0 > _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc index 0e6d5912a0..ab7c5caf86 100644 --- a/Platform/Hisilicon/D05/D05.dsc +++ b/Platform/Hisilicon/D05/D05.dsc @@ -305,13 +305,13 @@ gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize|0xbf0000 gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress|0xa9400000 gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize|0xbf0000 - gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress|0xa8800000 + gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress|0xa8000000 gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize|0x77f0000 gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionBaseAddress|0xab400000 gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize|0xbf0000 gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionBaseAddress|0xa9000000 gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize|0x2ff0000 - gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress|0xb0800000 + gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress|0xb0000000 gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize|0x77f0000 gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionBaseAddress|0xac900000 gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize|0x36f0000 @@ -336,10 +336,10 @@ gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase|0xA8400000 gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase|0xA9400000 - gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase|0xA8800000 + gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase|0xA8000000 gHisiTokenSpaceGuid.PcdHb0Rb3CpuMemRegionBase|0xAB400000 gHisiTokenSpaceGuid.PcdHb0Rb4CpuMemRegionBase|0x8A9000000 - gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase|0x8B0800000 + gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase|0x8B0000000 gHisiTokenSpaceGuid.PcdHb0Rb6CpuMemRegionBase|0x8AC900000 gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase|0x8B9800000 gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase|0x400A8400000 @@ -353,10 +353,10 @@ gHisiTokenSpaceGuid.PcdHb0Rb0CpuIoRegionBase|0xa8ff0000 gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase|0xa9ff0000 - gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase|0xafff0000 + gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase|0xaf7f0000 gHisiTokenSpaceGuid.PcdHb0Rb3CpuIoRegionBase|0xabff0000 gHisiTokenSpaceGuid.PcdHb0Rb4CpuIoRegionBase|0x8abff0000 - gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase|0x8b7ff0000 + gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase|0x8b77f0000 gHisiTokenSpaceGuid.PcdHb0Rb6CpuIoRegionBase|0x8afff0000 gHisiTokenSpaceGuid.PcdHb0Rb7CpuIoRegionBase|0x8bfff0000 gHisiTokenSpaceGuid.PcdHb1Rb0CpuIoRegionBase|0x400a8ff0000 diff --git a/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c b/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c index 57283a1053..ed6c4ac321 100644 --- a/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c +++ b/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c @@ -60,8 +60,8 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO /* Port 2 */ { PCI_HB0RB2_ECAM_BASE, - 0x80, //BusBase - 0x87, //BusLimit + 0xF8, //BusBase + 0xFF, //BusLimit PCI_HB0RB2_CPUMEMREGIONBASE ,//MemBase PCI_HB0RB2_CPUMEMREGIONBASE + PCI_HB0RB2_PCIREGION_SIZE - 1, //MemLimit (PCI_HB0RB2_IO_BASE), //IOBase @@ -106,8 +106,8 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO /* Port 5 */ { PCI_HB0RB5_ECAM_BASE,//ecam - 0x0, //BusBase - 0x7, //BusLimit + 0x78, //BusBase + 0x7F, //BusLimit PCI_HB0RB5_CPUMEMREGIONBASE, //Membase PCI_HB0RB5_CPUMEMREGIONBASE + PCI_HB0RB5_PCIREGION_SIZE - 1, //MemLimit (PCI_HB0RB5_IO_BASE), //IoBase diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl b/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl index 50ccac1b06..9955f6dbeb 100644 --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl +++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl @@ -412,9 +412,9 @@ [0004] ATS Attribute : 00000000 [0004] PCI Segment Number : 00000002 -[0004] Input base : 00008000 +[0004] Input base : 0000f800 [0004] ID Count : 00000800 -[0004] Output Base : 00008000 +[0004] Output Base : 0000f800 [0004] Output Reference : 00000064 [0004] Flags (decoded below) : 00000000 Single Mapping : 0 @@ -469,9 +469,9 @@ [0004] ATS Attribute : 00000000 [0004] PCI Segment Number : 00000005 -[0004] Input base : 00000000 +[0004] Input base : 00007800 [0004] ID Count : 00000800 -[0004] Output Base : 00000000 +[0004] Output Base : 00007800 [0004] Output Reference : 0000007c [0004] Flags (decoded below) : 00000000 Single Mapping : 0 diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc b/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc index b47cfec7bd..64807b1714 100644 --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc +++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc @@ -57,8 +57,8 @@ EFI_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE Mcfg= { 0xa0000000, //Base Address 0x2, //Segment Group Number - 0x80, //Start Bus Number - 0x87, //End Bus Number + 0xF8, //Start Bus Number + 0xFF, //End Bus Number 0x00000000, //Reserved }, //1p NB PCIe0 @@ -73,8 +73,8 @@ EFI_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE Mcfg= { 0x8b0000000, //Base Address 0x5, //Segment Group Number - 0x0, //Start Bus Number - 0x7, //End Bus Number + 0x78, //Start Bus Number + 0x7F, //End Bus Number 0x00000000, //Reserved }, //1p NB PCIe2 diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl index 122e4f072c..3f09e5e568 100644 --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl +++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl @@ -89,15 +89,15 @@ Scope(_SB) Name (_HID, "PNP0A08") // PCI Express Root Bridge Name (_CID, "PNP0A03") // Compatible PCI Root Bridge Name(_SEG, 2) // Segment of this Root complex - Name(_BBN, 0x80) // Base Bus Number + Name(_BBN, 0xF8) // Base Bus Number Name(_CCA, 1) Method (_CRS, 0, Serialized) { // Root complex resources Name (RBUF, ResourceTemplate () { WordBusNumber ( // Bus numbers assigned to this root ResourceProducer, MinFixed, MaxFixed, PosDecode, 0, // AddressGranularity - 0x80, // AddressMinimum - Minimum Bus Number - 0x87, // AddressMaximum - Maximum Bus Number + 0xF8, // AddressMinimum - Minimum Bus Number + 0xFF, // AddressMaximum - Maximum Bus Number 0, // AddressTranslation - Set to 0 0x8 // RangeLength - Number of Busses ) @@ -109,8 +109,8 @@ Scope(_SB) Cacheable, ReadWrite, 0x0, // Granularity - 0xa8800000, // Min Base Address - 0xaffeffff, // Max Base Address + 0xa8000000, // Min Base Address + 0xaf7effff, // Max Base Address 0x0, // Translate 0x77f0000 // Length ) @@ -123,7 +123,7 @@ Scope(_SB) 0x0, // Granularity 0x0, // Min Base Address 0xffff, // Max Base Address - 0xafff0000, // Translate + 0xaf7f0000, // Translate 0x10000 // Length ) }) // Name(RBUF) @@ -165,7 +165,7 @@ Scope(_SB) { Name (_HID, "PNP0C02") // Motherboard reserved resource Name (_CRS, ResourceTemplate (){ - Memory32Fixed (ReadWrite, 0xa8000000 , 0x800000) //ECAM space for [bus 80-87] + Memory32Fixed (ReadWrite, 0xaf800000 , 0x800000) //ECAM space for [bus f8-ff] }) Method (_STA, 0x0, NotSerialized) { @@ -280,15 +280,15 @@ Scope(_SB) Name (_HID, "PNP0A08") // PCI Express Root Bridge Name (_CID, "PNP0A03") // Compatible PCI Root Bridge Name(_SEG, 5) // Segment of this Root complex - Name(_BBN, 0x0) // Base Bus Number + Name(_BBN, 0x78) // Base Bus Number Name(_CCA, 1) Method (_CRS, 0, Serialized) { // Root complex resources Name (RBUF, ResourceTemplate () { WordBusNumber ( // Bus numbers assigned to this root ResourceProducer, MinFixed, MaxFixed, PosDecode, 0, // AddressGranularity - 0x0, // AddressMinimum - Minimum Bus Number - 0x7, // AddressMaximum - Maximum Bus Number + 0x78, // AddressMinimum - Minimum Bus Number + 0x7f, // AddressMaximum - Maximum Bus Number 0, // AddressTranslation - Set to 0 0x8 // RangeLength - Number of Busses ) @@ -300,8 +300,8 @@ Scope(_SB) Cacheable, ReadWrite, 0x0, // Granularity - 0xb0800000, // Min Base Address - 0xb7feffff, // Max Base Address + 0xb0000000, // Min Base Address + 0xb77effff, // Max Base Address 0x800000000, // Translate 0x77f0000 // Length ) @@ -314,7 +314,7 @@ Scope(_SB) 0x0, // Granularity 0x0, // Min Base Address 0xffff, // Max Base Address - 0x8b7ff0000, // Translate + 0x8b77f0000, // Translate 0x10000 // Length ) }) // Name(RBUF) @@ -593,7 +593,7 @@ Scope(_SB) 0x0, // Translate 0x800000 // Length ) - QwordMemory ( //ECAM space for [bus 0-7] + QwordMemory ( //ECAM space for [bus 78-7f] ResourceConsumer, PosDecode, MinFixed, @@ -601,8 +601,8 @@ Scope(_SB) NonCacheable, ReadWrite, 0x0, // Granularity - 0x8b0000000, // Min Base Address - 0x8b07fffff, // Max Base Address + 0x8b7800000, // Min Base Address + 0x8b7ffffff, // Max Base Address 0x0, // Translate 0x800000 // Length )