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[198.145.21.10]) by mx.google.com with ESMTPS id f12-v6si3447488pgn.459.2018.06.21.01.13.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 21 Jun 2018 01:13:23 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=kwCvtReE; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id CA6BA211DB43F; Thu, 21 Jun 2018 01:13:22 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::241; helo=mail-wr0-x241.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x241.google.com (mail-wr0-x241.google.com [IPv6:2a00:1450:400c:c0c::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id D3EF8211C8302 for ; Thu, 21 Jun 2018 01:13:21 -0700 (PDT) Received: by mail-wr0-x241.google.com with SMTP id f16-v6so2162696wrm.3 for ; Thu, 21 Jun 2018 01:13:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=R+Lo6Atv3Y/KMTl59+QeCsQFql15WuO17UHq1O9S9gw=; b=kwCvtReEylkLl5OyguPSlUeLkPTT7iJDDXiJhlHBSOfWsPX9dHY+m1KEbrYLh2CM2O jRUb5tae374DdHAElchMJaEOGllJFYSQfS6VEs5qGC90hH+A+LJUjYUdGVy/4cSeGlQJ 6t6PX0yp5JoFXwNxri6/GP2PznPDWmPLzPZIc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=R+Lo6Atv3Y/KMTl59+QeCsQFql15WuO17UHq1O9S9gw=; b=Wzwv7TC/9SRzjPYQ1ugrFPq6iuf4yBtk4Moo365cSViUjq3MsOiCuGGLjHN1QVPlKY 9kuDQpwE9nmbJ8MmHy4TXAZzSH2rO7PhpdQqDYLhNYPxWoyEB+EPz78Ld05ciOMl1f9G KT2eCJYau+rgFVoq6ykehyB6kXdO7v1tYkO54YrAQ5vy5nqO8C49AZBCuVPlvVYIGMgX upjPeF0yzPrnTV6Doxi6bY2llp+r85XnF2kGHZFG83XeIsa3jrccDlF5pzuGfjTlWkbR d/+vETOt65y8iFyO7xcr9C+M0SrfqCODlpXwXwrM+M0t7Die1FLiC1z5h36qfxVc3tSy ws6Q== X-Gm-Message-State: APt69E0luzOCoVMG6iPsWOLyFgYEXB6ePvrxczgIlvk0ZECU82sb5but OPCdHalEt1i42xEMBugF4EmOpK6UXWI= X-Received: by 2002:a5d:4306:: with SMTP id h6-v6mr21206260wrq.58.1529568800166; Thu, 21 Jun 2018 01:13:20 -0700 (PDT) Received: from dogfood.home ([2a01:cb1d:112:6f00:104b:ef1a:8c01:a5bb]) by smtp.gmail.com with ESMTPSA id q17-v6sm4803152wro.30.2018.06.21.01.13.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 21 Jun 2018 01:13:18 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Thu, 21 Jun 2018 10:13:14 +0200 Message-Id: <20180621081315.16228-2-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180621081315.16228-1-ard.biesheuvel@linaro.org> References: <20180621081315.16228-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH v2 1/2] ArmPkg/ArmMmuLib ARM: remove cache maintenance of block mapping contents X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Peculiarly enough, the current page table manipulation code takes it upon itself to write back and invalidate the memory contents covered by section mappings when their memory attributes change. It is not generally the case that data must be written back when such a change occurs, even when switching from cacheable to non-cacheable attributes, and in some cases, it is actually causing problems. (The cache maintenance is also performed on the PCIe MMIO regions as they get mapped by the PCI bus driver, and under virtualization, each cache maintenance operation on an emulated MMIO region triggers a round trip to the host and back) So let's just drop this code. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c | 12 ------------ 1 file changed, 12 deletions(-) -- 2.17.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c index 9bf4ba03fd5b..9c2578979e44 100644 --- a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c @@ -597,12 +597,6 @@ UpdatePageEntries ( if (CurrentPageTableEntry != PageTableEntry) { Mva = (VOID *)(UINTN)((((UINTN)FirstLevelIdx) << TT_DESCRIPTOR_SECTION_BASE_SHIFT) + (PageTableIndex << TT_DESCRIPTOR_PAGE_BASE_SHIFT)); - // Clean/invalidate the cache for this page, but only - // if we are modifying the memory type attributes - if (((CurrentPageTableEntry ^ PageTableEntry) & TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK) != 0) { - WriteBackInvalidateDataCacheRange (Mva, TT_DESCRIPTOR_PAGE_SIZE); - } - // Only need to update if we are changing the entry PageTable[PageTableIndex] = PageTableEntry; ArmUpdateTranslationTableEntry ((VOID *)&PageTable[PageTableIndex], Mva); @@ -718,12 +712,6 @@ UpdateSectionEntries ( if (CurrentDescriptor != Descriptor) { Mva = (VOID *)(UINTN)(((UINTN)FirstLevelIdx + i) << TT_DESCRIPTOR_SECTION_BASE_SHIFT); - // Clean/invalidate the cache for this section, but only - // if we are modifying the memory type attributes - if (((CurrentDescriptor ^ Descriptor) & TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK) != 0) { - WriteBackInvalidateDataCacheRange (Mva, SIZE_1MB); - } - // Only need to update if we are changing the descriptor FirstLevelTable[FirstLevelIdx + i] = Descriptor; ArmUpdateTranslationTableEntry ((VOID *)&FirstLevelTable[FirstLevelIdx + i], Mva);