From patchwork Tue Feb 27 09:20:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 129748 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp1171915lja; Tue, 27 Feb 2018 01:20:39 -0800 (PST) X-Google-Smtp-Source: AH8x226g/R3dnjaSZpH1oQslXilgF+6upK+MadIXbWORMpK0LJ+REL0P5XEC+y57KLzdkAMFozAj X-Received: by 10.98.28.202 with SMTP id c193mr13502926pfc.109.1519723238878; Tue, 27 Feb 2018 01:20:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519723238; cv=none; d=google.com; s=arc-20160816; b=O69bU8yK2lJ2d7Egs6Tf/UdSR2PElo41I8Sv5SuPqrtM6ZSYfybFRdH6kvLN4xz90C AP6jwAqB69cttFrh/7urRmGCFRLMR/dX0aQP1Ub2E9ELhBdO4OfftmkOpQ1HD1KCz39O FKWyvFn+nm7yD2c3loUzQwx5CPbHGBQ7HJDophG9pVEirIAl5BFwwWTW0pEJBlXqyeQn Qx7+Gm2BgfanejsTM1Rwhp4T0UXjGj0uImgBYvXGrM8r1mV5r+Ks2/u8qaHcJ4G9sI9V NtFQrWWWJy9TtuHObPwj3w+W+TWlWbcp7Cy2C4hDWeCB8Ngc6e1bAotvThPp7dU4Zknd /yww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=odRCNba0+CFnfP1StEN7zrjeg41A1/NPefbPDe0rDww=; b=dfAeMOi4gVPqG9hxZEhI4W+NSiEhqaNMPTM6PyTUgkArS0BjHh4Txt0T1bFz3Z+aVx 4tLgOY3PsJEdhYr2Kip1ynH3BZo6MF+pHLoo+u+DStaCgg89fJIKyA8Cc8YxSgbCXRJz ytxUykdvU7Afr0SrPNVNk6SkbARnT0YnIXb9XB3XsD75gWIUpS8l85Nhy0QfhYhw87lt d8v8GFjTxYBkUwoosedndMra5bAI20Ihz1mHBs/pSpVWkgggBMjbg9US23O9xu0Y6GhJ 5UxG/cIGoXrrzOEVdtSFbx9IXhgZMAWun5rWN8yRnw6n2/nBGBy3XPEjl4KtTXPs9Z7u egmQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=e/tt7zKi; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [198.145.21.10]) by mx.google.com with ESMTPS id l4-v6si8276012plb.68.2018.02.27.01.20.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 27 Feb 2018 01:20:38 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=e/tt7zKi; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 5F5F922436923; Tue, 27 Feb 2018 01:14:30 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::244; helo=mail-wm0-x244.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x244.google.com (mail-wm0-x244.google.com [IPv6:2a00:1450:400c:c09::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 64C6121F0DA69 for ; Tue, 27 Feb 2018 01:14:28 -0800 (PST) Received: by mail-wm0-x244.google.com with SMTP id q83so22687710wme.5 for ; Tue, 27 Feb 2018 01:20:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jht1mn39aaH/E23YCaHnzC+0qwJX69YfIrvPC6NlTkQ=; b=e/tt7zKiqeyT3Zt5qgO4v8qUgzPx7NGMAO8mMS5J9Rx/l/OY1ja8N+/1HspOsP/TD7 Kur4VJPfAY636i53XmrCq9ghDam7hi90jGXY07j4KlL3A9eSFo38NeRkjaSz5sqFlIsV J5G9ijlVh6mqt1nvpkabxlZV2RZvQ1VZ1PtfU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jht1mn39aaH/E23YCaHnzC+0qwJX69YfIrvPC6NlTkQ=; b=fEHrslmmeS0xL20MHJxncSovdht39oBV2gFj34znoNEfl/ZCJfkcNBTUnfXX0EcYBc 2tUfBiNgOC3vwVl28RnLUYJtGXSqVgX5RtV+bAXaTHCRLtXjfT6bLj2pEEoc/O1a1O9x Z8gQWzK/+seY2vKqtVkGLYKQikdXgPWTUcsmxasKgLQyvDZCY10bLhRwp1CrEZRFe575 t4gJG9pvUmPRWp7rzGF/HfLQd8i2uH9BPBVK6QjhIhBglSXUCverXsF+6jHZLzoteaBj gI33IYMPAu4a/PXQXRJ6DDMYo7+0BuJCZTEQJGvfPGjfEVvXXb3XgeNK7dwxxNW9zbac UyPw== X-Gm-Message-State: APf1xPA6/ddpOJRKlJDB5mAuD846oiw7cuOGjWzJrYTOxMHSqi+Plwjr dalxVHmWuY8mhEtn9anZxElVIm7Oe8c= X-Received: by 10.28.131.210 with SMTP id f201mr11043663wmd.117.1519723232701; Tue, 27 Feb 2018 01:20:32 -0800 (PST) Received: from localhost.localdomain ([160.167.215.215]) by smtp.gmail.com with ESMTPSA id x190sm12549865wme.27.2018.02.27.01.20.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 27 Feb 2018 01:20:32 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Tue, 27 Feb 2018 09:20:14 +0000 Message-Id: <20180227092017.23617-3-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180227092017.23617-1-ard.biesheuvel@linaro.org> References: <20180227092017.23617-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms 2/5] Silicon/SynQuacer: tweak PCI I/O windows for ACPI/Linux support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: masahisa.kojima@linaro.org, leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" ACPI is not able to describe PCI resource windows that involve both type and address translation (i.e., for I/O windows on architectures that do not support port I/O natively), and so the ACPI/Linux code has a hard time performing the resource allocation in such cases. For instance, the secondary I/O window we implement on SynQuacer: I/O 0x10000 ... 0x1ffff -> 0x77f00000 is misinterpreted by Linux, and results in the MMIO range starting at 0x77f10000 to be mapped for I/O port access to this range. This can be mitigated by using the same PCI range for I/O port access on both RCs., i.e., 0x0 ... 0xffff. This configuration can be represented using both DT and ACPI, and will work as expected in Linux, since it only involves type translation and not address translation. However, there is a downside: EDK2 does not cope with I/O address translation in the generic PCI host bridge driver, and so it does not allow two regions 0x0 ... 0xffff to be configured. So in addition, let's reduce the windows declared to the UEFI PCI layer to 0x0 ... 0x7fff and 0x8000 ... 0xffff. This leaves ample room for I/O BARs (which nobody uses anymore anyway), and allows UEFI and the OS to share the same static configuration of the PCIe BAR windows. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Heyi Gui is currently implementing support for address translation in the generic PCI host bridge driver, so hopefully, limiting the I/O ranges in UEFI is something we can revert shortly. Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 2 +- Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h | 18 +++++++++++------- Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c | 4 ++-- 3 files changed, 14 insertions(+), 10 deletions(-) -- 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi index 05d1673a5c2b..6eb5fd9430cb 100644 --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi @@ -483,7 +483,7 @@ bus-range = <0x0 0x7e>; #address-cells = <3>; #size-cells = <2>; - ranges = <0x1000000 0x00 0x00010000 0x00 0x77f00000 0x0 0x00010000>, + ranges = <0x1000000 0x00 0x00000000 0x00 0x77f00000 0x0 0x00010000>, <0x2000000 0x00 0x78000000 0x00 0x78000000 0x0 0x08000000>, <0x3000000 0x3f 0x00000000 0x3f 0x00000000 0x1 0x00000000>; diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h b/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h index 2d3d5cd91be0..ee57377ac3be 100644 --- a/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h +++ b/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h @@ -23,12 +23,12 @@ #define SYNQUACER_PCI_SEG0_BUSNUM_MIN 0x0 #define SYNQUACER_PCI_SEG0_BUSNUM_MAX 0x7e +#define SYNQUACER_PCI_SEG0_BUSNUM_RANGE 0x7f #define SYNQUACER_PCI_SEG0_PORTIO_MIN 0x0 -#define SYNQUACER_PCI_SEG0_PORTIO_MAX 0xffff -#define SYNQUACER_PCI_SEG0_PORTIO_SIZE 0x10000 +#define SYNQUACER_PCI_SEG0_PORTIO_MAX 0x7fff #define SYNQUACER_PCI_SEG0_PORTIO_MEMBASE 0x67f00000 -#define SYNQUACER_PCI_SEG0_PORTIO_MEMSIZE SYNQUACER_PCI_SEG0_PORTIO_SIZE +#define SYNQUACER_PCI_SEG0_PORTIO_MEMSIZE 0x10000 #define SYNQUACER_PCI_SEG0_MMIO32_MIN 0x68000000 #define SYNQUACER_PCI_SEG0_MMIO32_MAX 0x6fffffff @@ -45,12 +45,12 @@ #define SYNQUACER_PCI_SEG1_BUSNUM_MIN 0x0 #define SYNQUACER_PCI_SEG1_BUSNUM_MAX 0x7e +#define SYNQUACER_PCI_SEG1_BUSNUM_RANGE 0x7f -#define SYNQUACER_PCI_SEG1_PORTIO_MIN 0x10000 -#define SYNQUACER_PCI_SEG1_PORTIO_MAX 0x1ffff -#define SYNQUACER_PCI_SEG1_PORTIO_SIZE 0x10000 +#define SYNQUACER_PCI_SEG1_PORTIO_MIN 0x8000 +#define SYNQUACER_PCI_SEG1_PORTIO_MAX 0xffff #define SYNQUACER_PCI_SEG1_PORTIO_MEMBASE 0x77f00000 -#define SYNQUACER_PCI_SEG1_PORTIO_MEMSIZE SYNQUACER_PCI_SEG1_PORTIO_SIZE +#define SYNQUACER_PCI_SEG1_PORTIO_MEMSIZE 0x10000 #define SYNQUACER_PCI_SEG1_MMIO32_MIN 0x78000000 #define SYNQUACER_PCI_SEG1_MMIO32_MAX 0x7fffffff @@ -65,4 +65,8 @@ #define SYNQUACER_PCI_SLOT1_LOCATION SYNQUACER_PCI_LOCATION(0, 1, 3) #define SYNQUACER_PCI_SLOT2_LOCATION SYNQUACER_PCI_LOCATION(0, 1, 7) +#define SYNQUACER_PCI_OS_IO_BASE 0x0 +#define SYNQUACER_PCI_OS_IO_LIMIT 0xffff +#define SYNQUACER_PCI_OS_IO_RANGE 0x10000 + #endif diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c index e4679543cc66..6a3b32f6ca55 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c @@ -348,8 +348,8 @@ PciInitControllerPost ( // Region 3: port I/O range ConfigureWindow (DbiBase, 3, IoMemBase, - RootBridge->Io.Base, - RootBridge->Io.Limit - RootBridge->Io.Base + 1, + SYNQUACER_PCI_OS_IO_BASE, + SYNQUACER_PCI_OS_IO_RANGE, IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_IO, 0);