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[198.145.21.10]) by mx.google.com with ESMTPS id a8-v6si1940888ple.435.2018.02.23.07.41.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Feb 2018 07:41:25 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Og3rysB8; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id DDF51222630B5; Fri, 23 Feb 2018 07:35:18 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::241; helo=mail-wm0-x241.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x241.google.com (mail-wm0-x241.google.com [IPv6:2a00:1450:400c:c09::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3F9D8222630A6 for ; Fri, 23 Feb 2018 07:35:16 -0800 (PST) Received: by mail-wm0-x241.google.com with SMTP id z9so5336949wmb.3 for ; Fri, 23 Feb 2018 07:41:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=C9h/P1XCDiIkf3xZ0a2iQMrlBqEUmu5dkNvInLrGHM0=; b=Og3rysB8RmKgZ56P/tDHOjpP4dKf3ytXfSeBaSgxJ0kt/akFV0+q5ct2BcPAiqT2F5 M1r8Gj30lBVWjpR+/q+N+HtgLiw3TIasZqNCL9UUnKuiodDfVrRQzjw1f+Xjms61GDAl /mlihm6DvJYSNMjfh91ueHnaDA6FHPni4w9p0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=C9h/P1XCDiIkf3xZ0a2iQMrlBqEUmu5dkNvInLrGHM0=; b=S/PGDErFokJwpvurJY4d/2i3FnlloKwbnjm0R99FXaLOAA3Pl7Nj6mJ3ypLD1JHGlf BtNg2f741Axl/t49KJmChg7S8PzLzK5IvhJPxbUpNW/0VPIBinSkFrgzJ9K/quyHCBR5 XaWvWmsKq5fdffNHg2Y51fXqst4+84epv5Pn06aQJnMWO0i6bvp0uryNNDp/GlI28q43 707FN94fQB1NkX12vbKZ7pr+0D302HBjwbk+tjwjxZAu902rFG1j8qDdFnLaCrm3hjQf RK6ScakIP8ERrDpCo0hiISHcq84t3VFJLsx4WSWY/OFJUx5dhQYEo3eM8iCUMGaDktBa 6SBw== X-Gm-Message-State: APf1xPCm7xMtg8rZ/u61CnyClo0H4RkgGxoyq/Q3wdgbgD+2WtcpsNvN 65TR9bs5Vwl2BgCSZB856iUgW2swxvk= X-Received: by 10.28.116.14 with SMTP id p14mr2243500wmc.117.1519400476243; Fri, 23 Feb 2018 07:41:16 -0800 (PST) Received: from localhost.localdomain ([196.90.4.100]) by smtp.gmail.com with ESMTPSA id 188sm2273215wmg.29.2018.02.23.07.41.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Feb 2018 07:41:15 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Fri, 23 Feb 2018 15:40:52 +0000 Message-Id: <20180223154052.9828-7-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180223154052.9828-1-ard.biesheuvel@linaro.org> References: <20180223154052.9828-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms v3 6/6] Platform/Socionext/DeveloperBox: add 96Boards mezzanine support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Wire up the various drivers for the 96Boards LS connector and the optional Secure96 mezzanine board. Note that this includes a [Rule] update that allows .dtb binaries to be bundled with DXE drivers. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Platform/Socionext/DeveloperBox/DeveloperBox.dsc | 34 ++++++++++++++++++++ Platform/Socionext/DeveloperBox/DeveloperBox.fdf | 10 ++++++ Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c | 9 ++++++ Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf | 2 ++ 4 files changed, 55 insertions(+) -- 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc index 3c109b495fbc..afd0a4f59f00 100644 --- a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc +++ b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc @@ -31,6 +31,9 @@ [Defines] [BuildOptions] RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG -U_FORTIFY_SOURCE -D_FORTIFY_SOURCE=0 + # add ample padding to the DTC so we can apply 96boards mezzanine overlays + *_*_*_DTC_FLAGS = -p 1024 + [BuildOptions.common.EDKII.DXE_CORE,BuildOptions.common.EDKII.DXE_DRIVER,BuildOptions.common.EDKII.UEFI_DRIVER,BuildOptions.common.EDKII.UEFI_APPLICATION] GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000 @@ -396,6 +399,28 @@ [PcdsFixedAtBuild.common] !endif gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareRevision|$(BUILD_NUMBER) + # + # 96boards mezzanine support + # + g96BoardsTokenSpaceGuid.PcdI2c0Parent|"/i2c@51210000" + g96BoardsTokenSpaceGuid.PcdI2c0BusFrequencyHz|100000 + g96BoardsTokenSpaceGuid.PcdSpiParent|"/spi@54810000" + g96BoardsTokenSpaceGuid.PcdGpioParent|"/gpio@51000000" + g96BoardsTokenSpaceGuid.PcdGpioPolarity|0 + + g96BoardsTokenSpaceGuid.PcdGpioPinA|10 + g96BoardsTokenSpaceGuid.PcdGpioPinB|11 + g96BoardsTokenSpaceGuid.PcdGpioPinC|12 + g96BoardsTokenSpaceGuid.PcdGpioPinD|13 + g96BoardsTokenSpaceGuid.PcdGpioPinE|18 + g96BoardsTokenSpaceGuid.PcdGpioPinF|19 + g96BoardsTokenSpaceGuid.PcdGpioPinG|20 + g96BoardsTokenSpaceGuid.PcdGpioPinH|21 + g96BoardsTokenSpaceGuid.PcdGpioPinI|22 + g96BoardsTokenSpaceGuid.PcdGpioPinJ|23 + g96BoardsTokenSpaceGuid.PcdGpioPinK|24 + g96BoardsTokenSpaceGuid.PcdGpioPinL|25 + [PcdsPatchableInModule] gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0 gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0 @@ -642,6 +667,15 @@ [Components.common] SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.inf # + # 96board mezzanine support + # + Platform/96Boards/Secure96Dxe/Secure96Dxe.inf + Silicon/Atmel/AtSha204a/AtSha204aDxe.inf + Platform/96Boards/96BoardsI2cDxe/96BoardsI2cDxe.inf + Platform/96Boards/LsConnectorDxe/LsConnectorDxe.inf + + # # I2C # Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/SynQuacerI2cDxe.inf + MdeModulePkg/Bus/I2c/I2cDxe/I2cDxe.inf diff --git a/Platform/Socionext/DeveloperBox/DeveloperBox.fdf b/Platform/Socionext/DeveloperBox/DeveloperBox.fdf index b668f42c7962..130572009fd0 100644 --- a/Platform/Socionext/DeveloperBox/DeveloperBox.fdf +++ b/Platform/Socionext/DeveloperBox/DeveloperBox.fdf @@ -237,9 +237,18 @@ [FV.FvMain] } # + # 96board mezzanine support + # + INF Platform/96Boards/Secure96Dxe/Secure96Dxe.inf + INF Platform/96Boards/96BoardsI2cDxe/96BoardsI2cDxe.inf + INF Silicon/Atmel/AtSha204a/AtSha204aDxe.inf + INF Platform/96Boards/LsConnectorDxe/LsConnectorDxe.inf + + # # I2C # INF Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/SynQuacerI2cDxe.inf + INF MdeModulePkg/Bus/I2c/I2cDxe/I2cDxe.inf [FV.FVMAIN_COMPACT] FvAlignment = 16 @@ -421,6 +430,7 @@ [Rule.Common.DXE_DRIVER] DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi UI STRING="$(MODULE_NAME)" Optional + RAW BIN Optional |.dtb } [Rule.Common.DXE_RUNTIME_DRIVER] diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c index aab830dc3a5a..8787aa6288a7 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c @@ -313,6 +313,15 @@ PlatformDxeEntryPoint ( &Handle); ASSERT_EFI_ERROR (Status); + // + // Install the g96BoardsI2c0MasterGuid GUID onto the same handle, + // identifying I2C #1 on our SoC as I2C #0 on the 96boards low speed connector + // + Status = gBS->InstallProtocolInterface (&Handle, + &g96BoardsI2c0MasterGuid, + EFI_NATIVE_INTERFACE, NULL); + ASSERT_EFI_ERROR (Status); + SmmuEnableCoherentDma (); SetMmioTimerFrequency (); diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf index 49d9deee57ea..fca66799ebcb 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf @@ -34,6 +34,7 @@ [Packages] EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec + Platform/96Boards/96Boards.dec Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.dec Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.dec Silicon/Socionext/SynQuacer/SynQuacer.dec @@ -56,6 +57,7 @@ [LibraryClasses] UefiRuntimeServicesTableLib [Guids] + g96BoardsI2c0MasterGuid gEfiHiiPlatformSetupFormsetGuid gFdtTableGuid gNetsecNonDiscoverableDeviceGuid