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[2001:19d0:306:5::1]) by mx.google.com with ESMTPS id n2si3082993pgp.337.2017.11.17.11.04.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 17 Nov 2017 11:04:57 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Hwevbl13; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 17D062035BB2D; Fri, 17 Nov 2017 11:00:42 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::244; helo=mail-wr0-x244.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x244.google.com (mail-wr0-x244.google.com [IPv6:2a00:1450:400c:c0c::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id F0BDB21B00DE8 for ; Fri, 17 Nov 2017 11:00:40 -0800 (PST) Received: by mail-wr0-x244.google.com with SMTP id y42so2946112wrd.3 for ; Fri, 17 Nov 2017 11:04:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=qkp/3w8Tj9T6fF79bTunACeKpTLkdj8+imOA3LZQ8I8=; b=Hwevbl13LUBElXSa2NcM7B7rVX/Itz5KTxUuLCzcCRlRRTvFadVxKn4tQFjoEzBZ0W vFkZVcC6AYZUqYAgddGsmAtBMB1omHBO+u1YCG9VzBae4KR/iGOlypX1v4wycZAnKu7o rvwAKFdZg3hvyFFH08+iI1GU6tncCOSfYa5oA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=qkp/3w8Tj9T6fF79bTunACeKpTLkdj8+imOA3LZQ8I8=; b=jgwx+zvGDS76SWLGCmn6ZOk2CgXdn+OCKbLu+ef4NmGBO6HxY+wHnp5ui7tw/37opi qcPRj2DoevdUlQXG7gFwr1tzZV7GMyRjAlJOBP4Cxqv7PCI6LWoc0PqPf29Z2UiATnIA xGcgs/PSOLJBL+XJT5Y+A63/9KdHJkWA4IRwbL46SzEp3TnNB6oAAbzvPNhppztVIW0w LVMmFyh+9pI20Bb3l1jUH6+6S2eeAfUFC/3t1xptP7KxAuLf/bHh8c7l/NJKVrS8dJ4R jQqVTO2ECtMjALaKaJM8lmhuoouPc7ZnnUlIezy6SmEDHJjlTZL9QfhGe1WcpB569Wjg mQmQ== X-Gm-Message-State: AJaThX5U29cPFVbNe1LtRBLyigavALWZZswJYLdYIXx9+z5cQrCMF7lm ICvqWAvT60dc0YCv8L1Frsy71S1DLMY= X-Received: by 10.223.196.189 with SMTP id m58mr5595703wrf.7.1510945490139; Fri, 17 Nov 2017 11:04:50 -0800 (PST) Received: from localhost.localdomain ([160.167.170.128]) by smtp.gmail.com with ESMTPSA id c54sm7139022wra.84.2017.11.17.11.04.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 17 Nov 2017 11:04:49 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org Date: Fri, 17 Nov 2017 19:04:23 +0000 Message-Id: <20171117190423.19511-7-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171117190423.19511-1-ard.biesheuvel@linaro.org> References: <20171117190423.19511-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms v5 6/6] Platform/SynQuacerEvalBoard: add eMMC driver stack X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: masahisa.kojima@linaro.org, daniel.thompson@linaro.org, masami.hiramatsu@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Add the drivers required to use the onboard eMMC on the SynQuacer Evaluation Board. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- NOTE: still depends on EDK2 patches that are not merged yet v5: use UINT64* to refer to capability register Platform/Socionext/DeveloperBox/DeveloperBox.dsc | 1 + Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc | 8 + Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf | 7 + Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c | 201 ++++++++++++++++++++ Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c | 12 +- Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h | 37 ++++ Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf | 5 + 7 files changed, 263 insertions(+), 8 deletions(-) -- 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc index 5d3dec8ba3a8..7ca9fb104311 100644 --- a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc +++ b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc @@ -177,6 +177,7 @@ [LibraryClasses.common.DXE_DRIVER] # PciSegmentLib|Silicon/Socionext/SynQuacer/Library/SynQuacerPciSegmentLib/SynQuacerPciSegmentLib.inf PciHostBridgeLib|Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf + NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscoverableDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf [LibraryClasses.common.UEFI_APPLICATION] PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc index c8a9f39cd1ae..10da45ad2837 100644 --- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc +++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc @@ -176,6 +176,7 @@ [LibraryClasses.common.DXE_DRIVER] # PciSegmentLib|Silicon/Socionext/SynQuacer/Library/SynQuacerPciSegmentLib/SynQuacerPciSegmentLib.inf PciHostBridgeLib|Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf + NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscoverableDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf [LibraryClasses.common.UEFI_APPLICATION] PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf @@ -529,6 +530,13 @@ [Components.common] MdeModulePkg/Universal/EbcDxe/EbcDxe.inf # + # eMMC support + # + MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf + MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.inf + MdeModulePkg/Bus/Sd/EmmcDxe/EmmcDxe.inf + + # # AHCI Support # MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf index 4577bd316a1f..1599f8953008 100644 --- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf +++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf @@ -149,6 +149,13 @@ [FV.FvMain] INF MdeModulePkg/Universal/EbcDxe/EbcDxe.inf # + # eMMC support + # + INF MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf + INF MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.inf + INF MdeModulePkg/Bus/Sd/EmmcDxe/EmmcDxe.inf + + # # AHCI Support # INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c new file mode 100644 index 000000000000..9b1957e99907 --- /dev/null +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c @@ -0,0 +1,201 @@ + /** @file + SynQuacer DXE platform driver - eMMC support + + Copyright (c) 2017, Linaro, Ltd. All rights reserved.
+ + This program and the accompanying materials are licensed and made available + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +**/ + +#include "PlatformDxe.h" + +// F_SDH30 extended Controller registers +#define F_SDH30_AHB_CONFIG 0x100 +#define F_SDH30_AHB_BIGED BIT6 +#define F_SDH30_BUSLOCK_DMA BIT5 +#define F_SDH30_BUSLOCK_EN BIT4 +#define F_SDH30_SIN BIT3 +#define F_SDH30_AHB_INCR_16 BIT2 +#define F_SDH30_AHB_INCR_8 BIT1 +#define F_SDH30_AHB_INCR_4 BIT0 + +#define F_SDH30_TUNING_SETTING 0x108 +#define F_SDH30_CMD_CHK_DIS BIT16 + +#define F_SDH30_IO_CONTROL2 0x114 +#define F_SDH30_MSEL_O_1_8 BIT18 +#define F_SDH30_CRES_O_DN BIT19 + +#define F_SDH30_ESD_CONTROL 0x124 +#define F_SDH30_EMMC_RST BIT1 +#define F_SDH30_EMMC_HS200 BIT24 +#define F_SDH30_CMD_DAT_DELAY BIT9 + +#define F_SDH30_TUNING_SETTING 0x108 +#define F_SDH30_CMD_CHK_DIS BIT16 + +#define F_SDH30_IO_CONTROL2 0x114 +#define F_SDH30_MSEL_O_1_8 BIT18 +#define F_SDH30_CRES_O_DN BIT19 + +#define F_SDH30_ESD_CONTROL 0x124 +#define F_SDH30_EMMC_RST BIT1 +#define F_SDH30_EMMC_HS200 BIT24 +#define F_SDH30_CMD_DAT_DELAY BIT9 + +#define SD_HC_CLOCK_CTRL 0x2C +#define SYNQUACER_CLOCK_CTRL_VAL 0xBC01 + +#define SD_HC_CAP_SDR104 BIT33 + +#define ESD_CONTROL_RESET_DELAY (20 * 1000) +#define IO_CONTROL2_SETTLE_US 3000 + +STATIC EFI_HANDLE mSdMmcControllerHandle; + +/** + + Override function for SDHCI capability bits + + @param[in] ControllerHandle The EFI_HANDLE of the controller. + @param[in] Slot The 0 based slot index. + @param[in,out] SdMmcHcSlotCapability The SDHCI capability structure. + + @retval EFI_SUCCESS The override function completed successfully. + @retval EFI_NOT_FOUND The specified controller or slot does not exist. + @retval EFI_INVALID_PARAMETER SdMmcHcSlotCapability is NULL + +**/ +STATIC +EFI_STATUS +EFIAPI +SynQuacerSdMmcOverrideCapability ( + IN EFI_HANDLE ControllerHandle, + IN UINT8 Slot, + IN OUT UINT64 *SdMmcHcSlotCapability + ) +{ + ASSERT (ControllerHandle == mSdMmcControllerHandle); + ASSERT (Slot == 0); + + if (ControllerHandle != mSdMmcControllerHandle || Slot != 0) { + return EFI_NOT_FOUND; + } + + // + // Clear the SDR104 capability bit. This avoids the need for a HS200 tuning + // quirk that is difficult to support using the generic driver. + // + *SdMmcHcSlotCapability &= ~(UINT64)SD_HC_CAP_SDR104; + + return EFI_SUCCESS; +} + +/** + + Override function for SDHCI controller operations + + @param[in] ControllerHandle The EFI_HANDLE of the controller. + @param[in] Slot The 0 based slot index. + @param[in,out] HookType The type of operation and whether the + hook is invoked right before (pre) or + right after (post) + + @retval EFI_SUCCESS The override function completed successfully. + @retval EFI_NOT_FOUND The specified controller or slot does not exist. + @retval EFI_INVALID_PARAMETER HookType is invalid + +**/ +STATIC +EFI_STATUS +EFIAPI +SynQuacerSdMmcInvokeHook ( + IN EFI_HANDLE ControllerHandle, + IN UINT8 Slot, + IN SD_MMC_OVERRIDE_HOOK HookType + ) +{ + ASSERT (ControllerHandle == mSdMmcControllerHandle); + ASSERT (Slot == 0); + + if (ControllerHandle != mSdMmcControllerHandle || Slot != 0) { + return EFI_NOT_FOUND; + } + + switch (HookType) { + case SD_MMC_OVERRIDE_RESET_PRE_HOOK: + // Soft reset does not complete unless the clock is already enabled. + MmioWrite16 (SYNQUACER_EMMC_BASE + SD_HC_CLOCK_CTRL, + SYNQUACER_CLOCK_CTRL_VAL); + break; + + case SD_MMC_OVERRIDE_INIT_HOST_PRE_HOOK: + // init vendor specific regs + MmioAnd16 (SYNQUACER_EMMC_BASE + F_SDH30_AHB_CONFIG, + ~(F_SDH30_AHB_BIGED | F_SDH30_BUSLOCK_EN)); + + MmioOr16 (SYNQUACER_EMMC_BASE + F_SDH30_AHB_CONFIG, + F_SDH30_SIN | F_SDH30_AHB_INCR_16 | F_SDH30_AHB_INCR_8 | + F_SDH30_AHB_INCR_4); + + MmioAnd32 (SYNQUACER_EMMC_BASE + F_SDH30_ESD_CONTROL, ~F_SDH30_EMMC_RST); + MemoryFence (); + gBS->Stall (ESD_CONTROL_RESET_DELAY); + + MmioOr32 (SYNQUACER_EMMC_BASE + F_SDH30_ESD_CONTROL, + F_SDH30_EMMC_RST | F_SDH30_CMD_DAT_DELAY | F_SDH30_EMMC_HS200); + + gBS->Stall (IO_CONTROL2_SETTLE_US); + MmioOr32 (SYNQUACER_EMMC_BASE + F_SDH30_IO_CONTROL2, F_SDH30_CRES_O_DN); + MemoryFence (); + MmioOr32 (SYNQUACER_EMMC_BASE + F_SDH30_IO_CONTROL2, F_SDH30_MSEL_O_1_8); + MemoryFence (); + MmioAnd32 (SYNQUACER_EMMC_BASE + F_SDH30_IO_CONTROL2, ~F_SDH30_CRES_O_DN); + MemoryFence (); + gBS->Stall (IO_CONTROL2_SETTLE_US); + + MmioOr32 (SYNQUACER_EMMC_BASE + F_SDH30_TUNING_SETTING, + F_SDH30_CMD_CHK_DIS); + break; + + default: + break; + } + return EFI_SUCCESS; +} + +STATIC SD_MMC_OVERRIDE mSdMmcOverride = { + EDKII_SD_MMC_OVERRIDE_PROTOCOL_VERSION, + SynQuacerSdMmcOverrideCapability, + SynQuacerSdMmcInvokeHook, +}; + +EFI_STATUS +EFIAPI +RegisterEmmc ( + VOID + ) +{ + EFI_STATUS Status; + + Status = RegisterNonDiscoverableMmioDevice ( + NonDiscoverableDeviceTypeSdhci, + NonDiscoverableDeviceDmaTypeNonCoherent, + NULL, + &mSdMmcControllerHandle, + 1, + SYNQUACER_EMMC_BASE, SYNQUACER_EMMC_BASE_SZ); + ASSERT_EFI_ERROR (Status); + + Status = gBS->InstallProtocolInterface (&mSdMmcControllerHandle, + &gEdkiiSdMmcOverrideProtocolGuid, + EFI_NATIVE_INTERFACE, (VOID **)&mSdMmcOverride); + ASSERT_EFI_ERROR (Status); + + return EFI_SUCCESS; +} diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c index 070e6be92edd..c64ccf3b3c30 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c @@ -12,14 +12,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. **/ -#include -#include -#include -#include -#include -#include -#include -#include +#include "PlatformDxe.h" STATIC EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR mNetsecDesc[] = { { @@ -178,5 +171,8 @@ PlatformDxeEntryPoint ( &Handle); ASSERT_EFI_ERROR (Status); + Status = RegisterEmmc (); + ASSERT_EFI_ERROR (Status); + return EFI_SUCCESS; } diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h new file mode 100644 index 000000000000..e653d72d537c --- /dev/null +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h @@ -0,0 +1,37 @@ +/** @file + SynQuacer DXE platform driver. + + Copyright (c) 2017, Linaro, Ltd. All rights reserved.
+ + This program and the accompanying materials are licensed and made available + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +**/ + +#ifndef __PLATFORM_DXE_H__ +#define __PLATFORM_DXE_H__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +EFI_STATUS +EFIAPI +RegisterEmmc ( + VOID + ); + +#endif diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf index 478e0c7d33e9..8af79eeaa4bc 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf @@ -23,6 +23,7 @@ [Defines] ENTRY_POINT = PlatformDxeEntryPoint [Sources] + Emmc.c PlatformDxe.c [Packages] @@ -34,10 +35,13 @@ [Packages] Silicon/Socionext/SynQuacer/SynQuacer.dec [LibraryClasses] + BaseLib BaseMemoryLib DebugLib DtPlatformDtbLoaderLib + IoLib MemoryAllocationLib + NonDiscoverableDeviceRegistrationLib UefiBootServicesTableLib UefiDriverEntryPoint @@ -49,6 +53,7 @@ [Guids] [Protocols] gEdkiiNonDiscoverableDeviceProtocolGuid ## PRODUCES + gEdkiiSdMmcOverrideProtocolGuid ## PRODUCES gPcf8563RealTimeClockLibI2cMasterProtolGuid ## PRODUCES [FixedPcd]