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[2001:19d0:306:5::1]) by mx.google.com with ESMTPS id o88si3540688pfk.294.2017.11.17.11.04.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 17 Nov 2017 11:04:43 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=ARskilvS; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id DA94B2035BB2A; Fri, 17 Nov 2017 11:00:31 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::241; helo=mail-wm0-x241.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x241.google.com (mail-wm0-x241.google.com [IPv6:2a00:1450:400c:c09::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 5EC7721B00DD6 for ; Fri, 17 Nov 2017 11:00:30 -0800 (PST) Received: by mail-wm0-x241.google.com with SMTP id r68so8426278wmr.3 for ; Fri, 17 Nov 2017 11:04:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=H3Ah9Q8duy3Afg79EpzTv757fIkcBysSZkKdws+3v+I=; b=ARskilvS+G9YZiMowycA6oJYxEORnd10/mkXsNowV2w6srpAAFRyh2CxwAOug5VDYH O+W4sFNRjPPvepIAiFUvfmHnPhZFcefxrCvofd2TynClcepiOVX2/8y4hcCR4XfyM70G piLyZeJIb2u9kgvV+A+NSeyBgy6AprTrcoNW4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=H3Ah9Q8duy3Afg79EpzTv757fIkcBysSZkKdws+3v+I=; b=qd9ksW+iq4C5saO5wm1aFkuRYT2fOr51Gc020iU+vePHlUMOYKM7m095mG6BMQqKxl /Y2mD/53EaGOIJONzDf3BIqFFmMZRxP9CXU2/Tu7/8OZJNK7eC0aT+DbNBl6q9RkF3rO 0/v/9+yOXHZiu+kY8GyMEwAhzcahj3IJE5b9JhmtqGMCtXOEdZJt4JJ4yHvjGRN/37eP 6b9N4adInpEqNlhOeSJSh6loSTdHQNmYZvfwtz3TJoLZM+xIcLxOj9dxamUvByh0qHY6 vna+TQuKjLRPuvB4LZ4hSsDPvMZyvApjeziZxb1vgN1oTorTVOM0jLl27wPYzWmq7QtP TE5A== X-Gm-Message-State: AJaThX5OsWLKcsXsZ4aIN4dPG+H2ayENjwzFrFjiEPzlr+MCh/8O1t2A JcK23AQ3Bw+PTaak0Cdazl0N4HE3NxY= X-Received: by 10.28.221.138 with SMTP id u132mr4512552wmg.113.1510945479679; Fri, 17 Nov 2017 11:04:39 -0800 (PST) Received: from localhost.localdomain ([160.167.170.128]) by smtp.gmail.com with ESMTPSA id c54sm7139022wra.84.2017.11.17.11.04.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 17 Nov 2017 11:04:38 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org Date: Fri, 17 Nov 2017 19:04:19 +0000 Message-Id: <20171117190423.19511-3-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171117190423.19511-1-ard.biesheuvel@linaro.org> References: <20171117190423.19511-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms v5 2/6] Silicon/SynQuacer: add DT description of the SDHCI controller X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: masahisa.kojima@linaro.org, daniel.thompson@linaro.org, masami.hiramatsu@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Describe the SynQuacer SoC's eMMC controller in DT so the OS can attach to it. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- v5: disable by default, and only enable for the evaluation board Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 27 ++++++++++++++++++++ Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts | 4 +++ 2 files changed, 31 insertions(+) -- 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi index e72db377bc39..5e663c59efbd 100644 --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi @@ -532,4 +532,31 @@ #interrupt-cells = <3>; socionext,spi-base = <112>; }; + + clk_alw_b_0: bclk200 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + clock-output-names = "sd_bclk"; + }; + + clk_alw_c_0: sd4clk800 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <800000000>; + clock-output-names = "sd_sd4clk"; + }; + + sdhci: sdhci@52300000 { + compatible = "socionext,synquacer-sdhci", "fujitsu,mb86s70-sdhci-3.0"; + reg = <0 0x52300000 0x0 0x1000>; + interrupts = , + ; + bus-width = <8>; + cap-mmc-highspeed; + fujitsu,cmd-dat-delay-select; + clocks = <&clk_alw_c_0 &clk_alw_b_0>; + clock-names = "core", "iface"; + status = "disabled"; + }; }; diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts index 7de7db182b27..132fd370a71b 100644 --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts @@ -30,3 +30,7 @@ "NC", "NC", "PEC-PD26", "PEC-PD27", "PEC-PD28", "PEC-PD29", "PEC-PD30", "PEC-PD31"; }; + +&sdhci { + status = "okay"; +};