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[2001:19d0:306:5::1]) by mx.google.com with ESMTPS id b31si1345792plb.222.2017.10.31.03.52.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 31 Oct 2017 03:52:44 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=XLorphXo; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 6C7842034CF96; Tue, 31 Oct 2017 03:48:50 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::241; helo=mail-wm0-x241.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x241.google.com (mail-wm0-x241.google.com [IPv6:2a00:1450:400c:c09::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 6FA392034AB30 for ; Tue, 31 Oct 2017 03:48:46 -0700 (PDT) Received: by mail-wm0-x241.google.com with SMTP id y80so14696816wmd.0 for ; Tue, 31 Oct 2017 03:52:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=bf9tEhPMPL5zepj1H34xw9ll/6Fm7vNks127NQkQ+KA=; b=XLorphXoCIXKx+qhWYJn4Oli5JZttQGL65vC9WLoXlISBj5ilscgaE+4WMs10cSVEd 1d9D319wOPkIXCKlze1Dwis82Rdn8crcApSKNu/U5niM5OEGU4PxwF2+NSkfS/s/TeOL +xq6k2jDpavBxG2dqEgzBqcluOgo6gfigv1p8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=bf9tEhPMPL5zepj1H34xw9ll/6Fm7vNks127NQkQ+KA=; b=njIOERQhDBLI+hh3XrXFfrYQt4wcUI0BCd0yQKSamMby3q1BokZpyoJa8BHIYgwL9a o4q0QTLDdanR1i5Hj+vQb9nbsCHAtD90GFUEF6m9HgdmXmJ/MqRJXXYWfDpQp2eE3zIo LcnNvLzFLCdxkNbAkEAMYUCoQ4AuY0O8LiGaG+1LQyBTbML82d/bEqNQdBKte9rAt4wY PMpMSjusfJWX2yVYLfrBBBHDTFu0sM+oZGxaGAyQIyVW+PornPtoQJ8Y8Imbe0dgVbta qavzqhXbd9UJ+0Elr7ljtJNTtSHkzY0CyAK6zIBOJI3DQXCtnCie0Ld+TZoORwfnjtRR JCHw== X-Gm-Message-State: AMCzsaUawqYJJaUQvPWSt++errbjE89DZu8TL+bh0kfLLLHZVN4Qy28x BHLw28Au8r9jpaQoQmdlyePWgS+Xnik= X-Received: by 10.28.12.75 with SMTP id 72mr1443121wmm.133.1509447156209; Tue, 31 Oct 2017 03:52:36 -0700 (PDT) Received: from localhost.localdomain ([105.129.222.2]) by smtp.gmail.com with ESMTPSA id o14sm460985wra.54.2017.10.31.03.52.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 31 Oct 2017 03:52:35 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org Date: Tue, 31 Oct 2017 10:51:54 +0000 Message-Id: <20171031105218.30208-4-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171031105218.30208-1-ard.biesheuvel@linaro.org> References: <20171031105218.30208-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms v3 03/27] Silicon/Socionext: add PlatformPeilib implementation for SynQuacer X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: daniel.thompson@linaro.org, masami.hiramatsu@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Create a specialized PlatformPeiLib implementation that invokes the platform specific firmware interface (currently, just a data structure left in SRAM) to set the ARM standard PcdSystemMemoryBase|Size PCDs, and expose the information via a newly added DramInfo PPI. It is also in charge of copying the secondary compressed firmware volume to DRAM before decompressing it. This works around a performance issue regarding mapping the NOR flash with normal uncached attributes. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Silicon/Socionext/SynQuacer/Include/Platform/DramInfo.h | 30 ++++ Silicon/Socionext/SynQuacer/Include/Ppi/DramInfo.h | 64 ++++++++ Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.c | 161 ++++++++++++++++++++ Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.inf | 53 +++++++ Silicon/Socionext/SynQuacer/SynQuacer.dec | 12 ++ 5 files changed, 320 insertions(+) -- 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Leif Lindholm diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/DramInfo.h b/Silicon/Socionext/SynQuacer/Include/Platform/DramInfo.h new file mode 100644 index 000000000000..f7691bdade4a --- /dev/null +++ b/Silicon/Socionext/SynQuacer/Include/Platform/DramInfo.h @@ -0,0 +1,30 @@ +/** @file + Data structure for passing DRAM information from lower level firmware + + Copyright (c) 2017, Linaro Ltd. All rights reserved.
+ + This program and the accompanying materials are licensed and made available + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SYNQUACER_PLATFORM_DRAM_INFO_H_ +#define _SYNQUACER_PLATFORM_DRAM_INFO_H_ + +typedef struct { + UINT64 Base; + UINT64 Size; +} DRAM_INFO_ENTRY; + +typedef struct { + UINT32 NumRegions; + UINT32 Reserved; + DRAM_INFO_ENTRY Entry[3]; +} DRAM_INFO; + +#endif diff --git a/Silicon/Socionext/SynQuacer/Include/Ppi/DramInfo.h b/Silicon/Socionext/SynQuacer/Include/Ppi/DramInfo.h new file mode 100644 index 000000000000..6453e121317d --- /dev/null +++ b/Silicon/Socionext/SynQuacer/Include/Ppi/DramInfo.h @@ -0,0 +1,64 @@ +/** @file + DRAM info PPI to retrieve DRAM information from lower level firmware + + Copyright (c) 2017, Linaro Ltd. All rights reserved.
+ + This program and the accompanying materials are licensed and made available + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SYNQUACER_DRAMINFO_PPI_ +#define _SYNQUACER_DRAMINFO_PPI_ + +#define SYNQUACER_DRAMINFO_PPI_GUID \ + { 0x3e1d7356, 0xdda4, 0x4b1a, { 0x93, 0x46, 0xbf, 0x89, 0x1c, 0x86, 0x46, 0xcc } } + +/** + Retrieve the number of discontiguous DRAM regions + + @param[out] RegionCount The number of available DRAM regions + + @retval EFI_SUCCESS The data was successfully returned. + @retval EFI_INVALID_PARAMETER RegionCount == NULL + +**/ +typedef +EFI_STATUS +(EFIAPI * DRAMINFO_GET_REGION_COUNT) ( + OUT UINTN *RegionCount + ); + +/** + Retrieve the base and size of a DRAM region + + @param[in] RegionIndex The 0-based index of the region to retrieve + @param[out] Base The base of the requested region + @param[out] Size The size of the requested region + + @retval EFI_SUCCESS The data was successfully returned. + @retval EFI_INVALID_PARAMETER Base == NULL or Size == NULL + @retval EFI_NOT_FOUND No region exists with index >= RegionIndex + +**/ +typedef +EFI_STATUS +(EFIAPI * DRAMINFO_GET_REGION) ( + IN UINTN RegionIndex, + OUT UINT64 *Base, + OUT UINT64 *Size + ); + +typedef struct { + DRAMINFO_GET_REGION_COUNT GetRegionCount; + DRAMINFO_GET_REGION GetRegion; +} SYNQUACER_DRAM_INFO_PPI; + +extern EFI_GUID gSynQuacerDramInfoPpiGuid; + +#endif diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.c new file mode 100644 index 000000000000..d83f2ec524e5 --- /dev/null +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.c @@ -0,0 +1,161 @@ +/** @file +* +* Copyright (c) 2011-2014, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +STATIC +CONST DRAM_INFO *mDramInfo = (VOID *)(UINTN)FixedPcdGet64 (PcdDramInfoBase); + +/** + Retrieve the number of discontiguous DRAM regions + + @param[out] RegionCount The number of available DRAM regions + + @retval EFI_SUCCESS The data was successfully returned. + @retval EFI_INVALID_PARAMETER RegionCount == NULL + +**/ +STATIC +EFI_STATUS +EFIAPI +GetDramRegionCount ( + OUT UINTN *RegionCount + ) +{ + if (RegionCount == NULL) { + return EFI_INVALID_PARAMETER; + } + + *RegionCount = mDramInfo->NumRegions; + + return EFI_SUCCESS; +} + +/** + Retrieve the base and size of a DRAM region + + @param[in] RegionIndex The 0-based index of the region to retrieve + @param[out] Base The base of the requested region + @param[out] Size The size of the requested region + + @retval EFI_SUCCESS The data was successfully returned. + @retval EFI_INVALID_PARAMETER Base == NULL or Size == NULL + @retval EFI_NOT_FOUND No region exists with index >= RegionIndex + +**/ +STATIC +EFI_STATUS +EFIAPI +GetDramRegion ( + IN UINTN RegionIndex, + OUT UINT64 *Base, + OUT UINT64 *Size + ) +{ + if (Base == NULL || Size == NULL) { + return EFI_INVALID_PARAMETER; + } + + if (RegionIndex >= mDramInfo->NumRegions) { + return EFI_NOT_FOUND; + } + + *Base = mDramInfo->Entry[RegionIndex].Base; + *Size = mDramInfo->Entry[RegionIndex].Size; + + return EFI_SUCCESS; +} + +STATIC SYNQUACER_DRAM_INFO_PPI mDramInfoPpi = { + GetDramRegionCount, + GetDramRegion +}; + +STATIC CONST EFI_PEI_PPI_DESCRIPTOR mDramInfoPpiDescriptor = { + EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST, + &gSynQuacerDramInfoPpiGuid, + &mDramInfoPpi +}; + +STATIC +EFI_STATUS +EFIAPI +PeiMemoryDiscoveredNotify ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDesc, + IN VOID *Ppi + ) +{ + EFI_FIRMWARE_VOLUME_HEADER *Fvh; + VOID *Buf; + + Fvh = (EFI_FIRMWARE_VOLUME_HEADER *)(UINTN)FixedPcdGet64 (PcdSecondaryFvBase); + + Buf = AllocatePages (EFI_SIZE_TO_PAGES (Fvh->FvLength)); + if (Buf == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + DEBUG ((DEBUG_INFO, "%a: copying secondary FV to DRAM\n", __FUNCTION__)); + CopyMem (Buf, Fvh, Fvh->FvLength); + DEBUG ((DEBUG_INFO, "%a: copying done\n", __FUNCTION__)); + + PeiServicesInstallFvInfoPpi (NULL, Buf, Fvh->FvLength, NULL, NULL); + + return EFI_SUCCESS; +} + +STATIC CONST EFI_PEI_NOTIFY_DESCRIPTOR mPeiMemoryDiscoveredNotifyDesc = { + EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | + EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST, + &gEfiPeiMemoryDiscoveredPpiGuid, + PeiMemoryDiscoveredNotify +}; + +EFI_STATUS +EFIAPI +PlatformPeim ( + VOID + ) +{ + EFI_STATUS Status; + + ASSERT (mDramInfo->NumRegions > 0); + + // + // Record the first region into PcdSystemMemoryBase and PcdSystemMemorySize. + // This is the region we will use for UEFI itself. + // + Status = PcdSet64S (PcdSystemMemoryBase, mDramInfo->Entry[0].Base); + ASSERT_EFI_ERROR (Status); + + Status = PcdSet64S (PcdSystemMemorySize, mDramInfo->Entry[0].Size); + ASSERT_EFI_ERROR (Status); + + BuildFvHob (FixedPcdGet64 (PcdFvBaseAddress), FixedPcdGet32 (PcdFvSize)); + + Status = PeiServicesNotifyPpi (&mPeiMemoryDiscoveredNotifyDesc); + ASSERT_EFI_ERROR (Status); + + return PeiServicesInstallPpi (&mDramInfoPpiDescriptor); +} diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.inf b/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.inf new file mode 100644 index 000000000000..9a3fcebee394 --- /dev/null +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.inf @@ -0,0 +1,53 @@ +#/** @file +# +# Copyright (c) 2017, Linaro, Ltd. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = SynQuacerPlatformPeiLib + FILE_GUID = 86537337-b62b-4dcd-846f-033a6a8355e0 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = PlatformPeiLib + +[Sources] + SynQuacerPlatformPeiLib.c + +[Packages] + ArmPkg/ArmPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Socionext/SynQuacer/SynQuacer.dec + +[LibraryClasses] + BaseMemoryLib + DebugLib + HobLib + MemoryAllocationLib + PcdLib + PeiServicesLib + +[FixedPcd] + gArmTokenSpaceGuid.PcdFvBaseAddress + gArmTokenSpaceGuid.PcdFvSize + gSynQuacerTokenSpaceGuid.PcdDramInfoBase + +[Ppis] + gEfiPeiMemoryDiscoveredPpiGuid ## CONSUMES + gSynQuacerDramInfoPpiGuid ## PRODUCES + +[Pcd] + gArmTokenSpaceGuid.PcdSystemMemoryBase + gArmTokenSpaceGuid.PcdSystemMemorySize + gSynQuacerTokenSpaceGuid.PcdSecondaryFvBase + gSynQuacerTokenSpaceGuid.PcdSecondaryFvSize diff --git a/Silicon/Socionext/SynQuacer/SynQuacer.dec b/Silicon/Socionext/SynQuacer/SynQuacer.dec index c3adf85d3562..446be69473fb 100644 --- a/Silicon/Socionext/SynQuacer/SynQuacer.dec +++ b/Silicon/Socionext/SynQuacer/SynQuacer.dec @@ -18,3 +18,15 @@ [Defines] [Includes] Include + +[Guids] + gSynQuacerTokenSpaceGuid = { 0x4d04555b, 0xdfdc, 0x418a, { 0x8a, 0xab, 0x07, 0xce, 0xef, 0x46, 0x82, 0xbb } } + +[Ppis] + gSynQuacerDramInfoPpiGuid = { 0x3e1d7356, 0xdda4, 0x4b1a, { 0x93, 0x46, 0xbf, 0x89, 0x1c, 0x86, 0x46, 0xcc } } + +[PcdsFixedAtBuild] + gSynQuacerTokenSpaceGuid.PcdDramInfoBase|0|UINT64|0x00000001 + + gSynQuacerTokenSpaceGuid.PcdSecondaryFvBase|0|UINT64|0x00000002 + gSynQuacerTokenSpaceGuid.PcdSecondaryFvSize|0|UINT64|0x00000003