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[2001:19d0:306:5::1]) by mx.google.com with ESMTPS id z3si1344624pln.173.2017.10.31.03.54.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 31 Oct 2017 03:54:47 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=HLFCgd1O; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 4444D2035D110; Tue, 31 Oct 2017 03:49:46 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::243; helo=mail-wm0-x243.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x243.google.com (mail-wm0-x243.google.com [IPv6:2a00:1450:400c:c09::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3BC732035D106 for ; Tue, 31 Oct 2017 03:49:45 -0700 (PDT) Received: by mail-wm0-x243.google.com with SMTP id b189so21462921wmd.4 for ; Tue, 31 Oct 2017 03:53:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4JTKSoExu5+JIIS9F4rQmWXNvc8yJBzg4rCh+wSBDPk=; b=HLFCgd1Oa/BA9WK7/VLFYnVAt/4yfPBqcnu6Hyr3v4ohhAHWly/m99AXsPYaTxJ2+e E2cjacy33qXdU9P8xatEyA4SyiYgpRLDYegOssVgicoChikgJQjtFYf0aMPKtUbYZ/t5 6QHgNURtfOKcchspHb/fcxW0ffY5tC2onTf+s= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4JTKSoExu5+JIIS9F4rQmWXNvc8yJBzg4rCh+wSBDPk=; b=EzJvE3OOXBP9drsXVfKvzR7pUAyynjBc7FQZVnnGR2146Me4LQw4ayVybhoR8TdeQ+ Pr9HaE3UhjD9JZ6iNs4LjoObCPNWVJkRjpDPAcneQ3NhY5Nao0p8zX0KISKfjEUfdkeN xxPY45Uu4Te5qHYBrzdoVVgLBllVevU41KEnbsA2bYDYztvfLOEJsRQqh5gaaetM2Zrx hcff84+S4B03siKLs8G9TcBdwqUXo+VLb5qRCqvzv9T4A90/9o3FGBv/Uy5xU7My2tFc mmYBSxUqgghfcZDaoCg4qHatoL8x07J4l6ZENMPhKlzihuNLOkHKismNuEDbxS2DBwJy 0U+g== X-Gm-Message-State: AMCzsaXw/JPN+nouE/YVflSalVdivxWj0/TsgWgku6BePIfJDCSfxXfR OlleVqmenYWeKoD1oLd21rIdFRpR+K4= X-Received: by 10.28.12.75 with SMTP id 72mr1445385wmm.133.1509447215311; Tue, 31 Oct 2017 03:53:35 -0700 (PDT) Received: from localhost.localdomain ([105.129.222.2]) by smtp.gmail.com with ESMTPSA id o14sm460985wra.54.2017.10.31.03.53.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 31 Oct 2017 03:53:34 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org Date: Tue, 31 Oct 2017 10:52:17 +0000 Message-Id: <20171031105218.30208-27-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171031105218.30208-1-ard.biesheuvel@linaro.org> References: <20171031105218.30208-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms v3 26/27] Silicon/SynQuacer: add description of GPIO block to device tree X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: daniel.thompson@linaro.org, masami.hiramatsu@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Add a description of the SoCs GPIO controller as well as a description of DIP switch block #3, which is wired to GPIOs 0 - 7, both on the evaluation board as well as the Developer Box. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts | 50 ++++++++++++++++++++ Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 12 +++++ Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts | 50 ++++++++++++++++++++ 3 files changed, 112 insertions(+) -- 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Leif Lindholm diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts b/Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts index 9e0acd593311..791e690adccd 100644 --- a/Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts +++ b/Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts @@ -19,3 +19,53 @@ model = "Socionext Developer Box"; compatible = "socionext,developer-box", "socionext,synquacer"; }; + +&gpio { + dsw3_1 { + gpios = <0 GPIO_ACTIVE_HIGH>; + gpio-hog; + input; + }; + + dsw3_2 { + gpios = <1 GPIO_ACTIVE_HIGH>; + gpio-hog; + input; + }; + + dsw3_3 { + gpios = <2 GPIO_ACTIVE_HIGH>; + gpio-hog; + input; + }; + + dsw3_4 { + gpios = <3 GPIO_ACTIVE_HIGH>; + gpio-hog; + input; + }; + + dsw3_5 { + gpios = <4 GPIO_ACTIVE_HIGH>; + gpio-hog; + input; + }; + + dsw3_6 { + gpios = <5 GPIO_ACTIVE_HIGH>; + gpio-hog; + input; + }; + + dsw3_7 { + gpios = <6 GPIO_ACTIVE_HIGH>; + gpio-hog; + input; + }; + + dsw3_8 { + gpios = <7 GPIO_ACTIVE_HIGH>; + gpio-hog; + input; + }; +}; diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi index 3aef10294662..0746b7853ebf 100644 --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi @@ -21,6 +21,9 @@ #define IRQ_TYPE_LEVEL_HIGH 4 #define IRQ_TYPE_LEVEL_LOW 8 +#define GPIO_ACTIVE_HIGH 0 +#define GPIO_ACTIVE_LOW 1 + / { #address-cells = <2>; #size-cells = <2>; @@ -511,4 +514,13 @@ msi-map = <0x0 &its 0x10000 0x7f00>; dma-coherent; }; + + gpio: gpio@51000000 { + compatible = "socionext,sc2a11-gpio", "fujitsu,mb86s70-gpio"; + reg = <0x0 0x51000000 0x0 0x100>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clk_apb>; + base = <0>; + }; }; diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts index cda72fdf2f99..062c1e5eeeb1 100644 --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts @@ -19,3 +19,53 @@ model = "SynQuacer Evaluation Board"; compatible = "socionext,synquacer-eval-board", "socionext,synquacer"; }; + +&gpio { + dsw3_1 { + gpios = <0 GPIO_ACTIVE_HIGH>; + gpio-hog; + input; + }; + + dsw3_2 { + gpios = <1 GPIO_ACTIVE_HIGH>; + gpio-hog; + input; + }; + + dsw3_3 { + gpios = <2 GPIO_ACTIVE_HIGH>; + gpio-hog; + input; + }; + + dsw3_4 { + gpios = <3 GPIO_ACTIVE_HIGH>; + gpio-hog; + input; + }; + + dsw3_5 { + gpios = <4 GPIO_ACTIVE_HIGH>; + gpio-hog; + input; + }; + + dsw3_6 { + gpios = <5 GPIO_ACTIVE_HIGH>; + gpio-hog; + input; + }; + + dsw3_7 { + gpios = <6 GPIO_ACTIVE_HIGH>; + gpio-hog; + input; + }; + + dsw3_8 { + gpios = <7 GPIO_ACTIVE_HIGH>; + gpio-hog; + input; + }; +};