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[2001:19d0:306:5::1]) by mx.google.com with ESMTPS id 1si1293432plz.723.2017.10.31.03.52.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 31 Oct 2017 03:52:32 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Lsz6kdVG; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 9E9D22034AB3B; Tue, 31 Oct 2017 03:48:40 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::243; helo=mail-wr0-x243.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x243.google.com (mail-wr0-x243.google.com [IPv6:2a00:1450:400c:c0c::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 1F5D62034AB1B for ; Tue, 31 Oct 2017 03:48:38 -0700 (PDT) Received: by mail-wr0-x243.google.com with SMTP id z55so15527805wrz.1 for ; Tue, 31 Oct 2017 03:52:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=9mcqBoOhGUryLeKLVgMJM0OJbb3PL3DSNxz6uBVErTg=; b=Lsz6kdVGPze7yUenZ4GORdzD7Lv9jAXAx8inJRgARlrhZLidyneiIO0VICU10jkGZx wdl2vnac8HC9YkURybsd2J27IOximAjwj7nbjM1vZXcgHpNJrMxOB6NTYogWPzhS5Y3l NFJTeJC31OafYT/mz63CrB9G4JsdPV2Gpetuo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=9mcqBoOhGUryLeKLVgMJM0OJbb3PL3DSNxz6uBVErTg=; b=dJiELB53Hqa6VqDnKgmY9fOufn7hdWKg+1Why+cxOAdL5Mfe5GlxGEu2z9CZcKR5HO YHBxLZEPDdWqEFp7G5dW0MOdLukbWTnujOCFt4tgBsY3IoDZLlaUxrtqfQOzx1d6+AKh gRn0oIfS2KYbg//qsyMF46/gaA7TcRaDjsNPgZbhZEUFlP5A2EWuTLVNLxjFM4CjNQ83 hBuLpUD/8TXz4PfV1MfqZzIlxEl58QQwReBtnMWQ4KuVJj4aziMH+nkA2T1zGO8sze2k aOZYOnFbOiJmMBqUqRDSt2BHagrFvy8hrC5FHs5yxItDBLdQ2poF/4zqCVyWF2TToT+y 2czQ== X-Gm-Message-State: AMCzsaUpB+mmxwkD4x3hY/HSOoomhPVV/wvQeYklDK1ICtbCu7ZVsEYC JXh8qcBQlbImUendKwm8mJ30HpZ4i64= X-Received: by 10.223.175.232 with SMTP id y40mr1466503wrd.207.1509447148829; Tue, 31 Oct 2017 03:52:28 -0700 (PDT) Received: from localhost.localdomain ([105.129.222.2]) by smtp.gmail.com with ESMTPSA id o14sm460985wra.54.2017.10.31.03.52.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 31 Oct 2017 03:52:28 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org Date: Tue, 31 Oct 2017 10:51:52 +0000 Message-Id: <20171031105218.30208-2-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171031105218.30208-1-ard.biesheuvel@linaro.org> References: <20171031105218.30208-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms v3 01/27] Silicon/SynQuacer: add package with platform headers X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: daniel.thompson@linaro.org, masami.hiramatsu@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Add a package .DEC description for SynQuacer with an [Includes] section, and add header files containing descriptions of the platform's memory map and PCIe configuration. No code yet. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h | 60 +++++++++++++++++++ Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h | 63 ++++++++++++++++++++ Silicon/Socionext/SynQuacer/SynQuacer.dec | 20 +++++++ 3 files changed, 143 insertions(+) -- 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h b/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h new file mode 100644 index 000000000000..1ccd3122cdda --- /dev/null +++ b/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h @@ -0,0 +1,60 @@ +/** @file + Physical memory map for SynQuacer + + Copyright (c) 2017, Linaro Ltd. All rights reserved.
+ + This program and the accompanying materials are licensed and made available + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SYNQUACER_PLATFORM_MEMORYMAP_H_ +#define _SYNQUACER_PLATFORM_MEMORYMAP_H_ + +// Memory mapped SPI NOR +#define SYNQUACER_SPI_NOR_BASE 0x08000000 +#define SYNQUACER_SPI_NOR_SIZE SIZE_128MB + +// On-Chip non-secure ROM +#define SYNQUACER_NON_SECURE_ROM_BASE 0x1F000000 +#define SYNQUACER_NON_SECURE_ROM_SZ SIZE_512KB + +// On-Chip Peripherals +#define SYNQUACER_PERIPHERALS_BASE 0x20000000 +#define SYNQUACER_PERIPHERALS_SZ 0x0E000000 + +// On-Chip non-secure SRAM +#define SYNQUACER_NON_SECURE_SRAM_BASE 0x2E000000 +#define SYNQUACER_NON_SECURE_SRAM_SZ SIZE_64KB + +// GIC-500 +#define SYNQUACER_GIC500_DIST_BASE FixedPcdGet64 (PcdGicDistributorBase) +#define SYNQUACER_GIC500_DIST_SIZE SIZE_256KB +#define SYNQUACER_GIC500_RDIST_BASE FixedPcdGet64 (PcdGicRedistributorsBase) +#define SYNQUACER_GIC500_RDIST_SIZE SIZE_8MB + +// GPIO block +#define SYNQUACER_GPIO_BASE 0x51000000 +#define SYNQUACER_GPIO_SIZE SIZE_4KB + +// eMMC(SDH30) +#define SYNQUACER_EMMC_BASE 0x52300000 +#define SYNQUACER_EMMC_BASE_SZ SIZE_4KB + +#define SYNQUACER_EEPROM_BASE 0x10000000 +#define SYNQUACER_EEPROM_BASE_SZ SIZE_64KB + +// NETSEC +#define SYNQUACER_NETSEC_BASE 0x522D0000 +#define SYNQUACER_NETSEC_BASE_SZ SIZE_64KB + +// PCI +#define SYNQUACER_PCIE_BASE 0x58200000 +#define SYNQUACER_PCIE_SIZE 0x00200000 + +#endif diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h b/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h new file mode 100644 index 000000000000..d2a3f9acbf49 --- /dev/null +++ b/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h @@ -0,0 +1,63 @@ +/** @file + PCI memory configuration for SynQuacer + + Copyright (c) 2017, Linaro Ltd. All rights reserved.
+ + This program and the accompanying materials are licensed and made available + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SYNQUACER_PLATFORM_PCI_H_ +#define _SYNQUACER_PLATFORM_PCI_H_ + +#define SYNQUACER_PCI_SEG0_CONFIG_BASE 0x60000000 +#define SYNQUACER_PCI_SEG0_CONFIG_SIZE 0x07f00000 +#define SYNQUACER_PCI_SEG0_DBI_BASE 0x583d0000 +#define SYNQUACER_PCI_SEG0_EXS_BASE 0x58390000 + +#define SYNQUACER_PCI_SEG0_BUSNUM_MIN 0x0 +#define SYNQUACER_PCI_SEG0_BUSNUM_MAX 0x7e + +#define SYNQUACER_PCI_SEG0_PORTIO_MIN 0x0 +#define SYNQUACER_PCI_SEG0_PORTIO_MAX 0xffff +#define SYNQUACER_PCI_SEG0_PORTIO_SIZE 0x10000 +#define SYNQUACER_PCI_SEG0_PORTIO_MEMBASE 0x67f00000 +#define SYNQUACER_PCI_SEG0_PORTIO_MEMSIZE SYNQUACER_PCI_SEG0_PORTIO_SIZE + +#define SYNQUACER_PCI_SEG0_MMIO32_MIN 0x68000000 +#define SYNQUACER_PCI_SEG0_MMIO32_MAX 0x6fffffff +#define SYNQUACER_PCI_SEG0_MMIO32_SIZE 0x08000000 + +#define SYNQUACER_PCI_SEG0_MMIO64_MIN 0x3e00000000 +#define SYNQUACER_PCI_SEG0_MMIO64_MAX 0x3effffffff +#define SYNQUACER_PCI_SEG0_MMIO64_SIZE 0x100000000 + +#define SYNQUACER_PCI_SEG1_CONFIG_BASE 0x70000000 +#define SYNQUACER_PCI_SEG1_CONFIG_SIZE 0x07f00000 +#define SYNQUACER_PCI_SEG1_DBI_BASE 0x583c0000 +#define SYNQUACER_PCI_SEG1_EXS_BASE 0x58380000 + +#define SYNQUACER_PCI_SEG1_BUSNUM_MIN 0x0 +#define SYNQUACER_PCI_SEG1_BUSNUM_MAX 0x7e + +#define SYNQUACER_PCI_SEG1_PORTIO_MIN 0x10000 +#define SYNQUACER_PCI_SEG1_PORTIO_MAX 0x1ffff +#define SYNQUACER_PCI_SEG1_PORTIO_SIZE 0x10000 +#define SYNQUACER_PCI_SEG1_PORTIO_MEMBASE 0x77f00000 +#define SYNQUACER_PCI_SEG1_PORTIO_MEMSIZE SYNQUACER_PCI_SEG1_PORTIO_SIZE + +#define SYNQUACER_PCI_SEG1_MMIO32_MIN 0x78000000 +#define SYNQUACER_PCI_SEG1_MMIO32_MAX 0x7fffffff +#define SYNQUACER_PCI_SEG1_MMIO32_SIZE 0x08000000 + +#define SYNQUACER_PCI_SEG1_MMIO64_MIN 0x3f00000000 +#define SYNQUACER_PCI_SEG1_MMIO64_MAX 0x3fffffffff +#define SYNQUACER_PCI_SEG1_MMIO64_SIZE 0x100000000 + +#endif diff --git a/Silicon/Socionext/SynQuacer/SynQuacer.dec b/Silicon/Socionext/SynQuacer/SynQuacer.dec new file mode 100644 index 000000000000..c3adf85d3562 --- /dev/null +++ b/Silicon/Socionext/SynQuacer/SynQuacer.dec @@ -0,0 +1,20 @@ +# +# Copyright (c) 2017, Linaro, Ltd. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + +[Defines] + DEC_SPECIFICATION = 0x0001001A + PACKAGE_NAME = SynQuacer + PACKAGE_GUID = 9c782fd2-7db1-438d-b51c-2155cee2c5cc + PACKAGE_VERSION = 0.1 + +[Includes] + Include