| Message ID | 20171025175947.22798-22-ard.biesheuvel@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | add support for Socionext Synquacer | expand |
On Wed, Oct 25, 2017 at 06:59:45PM +0100, Ard Biesheuvel wrote: > Implement workaround suggested by Socionext to get legacy endpoints with > 32-bit BARs working. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> This was the modification that made the Developerbox onboard AHCI work? Worth mentioning explicitly if so. Regardless: Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> > --- > Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c | 8 ++++++-- > 1 file changed, 6 insertions(+), 2 deletions(-) > > diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c > index 3c6eff602f74..dd6c9bf90223 100644 > --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c > +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c > @@ -31,10 +31,13 @@ > #define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_IO 0x2 > #define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG0 0x4 > #define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG1 0x5 > +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH BIT12 > > #define IATU_REGION_CTRL_2_OFF_OUTBOUND_0 0x908 > #define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN BIT31 > #define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE BIT28 > +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_32BIT 0xF > +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_64BIT 0xFF > > #define IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0 0x90C > #define IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0 0x910 > @@ -296,8 +299,9 @@ PciInitController ( > RootBridge->Mem.Base, > RootBridge->Mem.Base, > RootBridge->Mem.Limit - RootBridge->Mem.Base + 1, > - IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM, > - 0); > + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM | > + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH, > + IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_32BIT); > > // Region 1: Type 0 config space > ConfigureWindow (DbiBase, 1, > -- > 2.11.0 > _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c index 3c6eff602f74..dd6c9bf90223 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c @@ -31,10 +31,13 @@ #define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_IO 0x2 #define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG0 0x4 #define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG1 0x5 +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH BIT12 #define IATU_REGION_CTRL_2_OFF_OUTBOUND_0 0x908 #define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN BIT31 #define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE BIT28 +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_32BIT 0xF +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_64BIT 0xFF #define IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0 0x90C #define IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0 0x910 @@ -296,8 +299,9 @@ PciInitController ( RootBridge->Mem.Base, RootBridge->Mem.Base, RootBridge->Mem.Limit - RootBridge->Mem.Base + 1, - IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM, - 0); + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM | + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH, + IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_32BIT); // Region 1: Type 0 config space ConfigureWindow (DbiBase, 1,
Implement workaround suggested by Socionext to get legacy endpoints with 32-bit BARs working. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> --- Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) -- 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel