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[2001:19d0:306:5::1]) by mx.google.com with ESMTPS id u62si851875pgd.634.2017.09.21.04.07.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 21 Sep 2017 04:07:44 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=gQJgw2cR; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id B5F0B21E94615; Thu, 21 Sep 2017 04:04:20 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received: from mail-pf0-x235.google.com (mail-pf0-x235.google.com [IPv6:2607:f8b0:400e:c00::235]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 5109F21E1B76D for ; Thu, 21 Sep 2017 04:04:19 -0700 (PDT) Received: by mail-pf0-x235.google.com with SMTP id g65so3046156pfe.13 for ; Thu, 21 Sep 2017 04:07:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ywMvyfRsnBRKbX1Stzg36amkLTumLotSxj7XV7C+m5E=; b=gQJgw2cRqgHtTxq6bKp5uYHgOImuQRFFQTAkXKgi3ijk6KjAOhdnM9o2xliXWniwZS 7z5+y8UC68clKBIeYAgQD2+8ejUL+5W2ESv917F5mMW86KWfDZKKIcxJ+ucFOSQwI8g6 Q3B9mV8c1eTw5AB62Oo8Vvrd7/MCIEDq1lvjs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ywMvyfRsnBRKbX1Stzg36amkLTumLotSxj7XV7C+m5E=; b=LYyZsLAzF8JI/4HIS5QiD6/Ei1kYVyyQkqgOEtDQ4SpGESwTq51e0CKG+Z0LnruFsb MJGS06ManDqdOhd8XAtZBN6dE7X0rkt95ZPNy1+gIYTDctUCMvgv12piw43eH2X5eJvA Vr4KUL4n8CA4I5V4eToCk39AYl36va1WWTBnzSeq5q1DabdjNs7Cf7zYCCFPABvYqdfc blcf/Y04s1/hfwgiugbxT3d5K8U3ktl8fFM+A01IJG6Cb/Y0VehR23cQaf+KQAcjUQjf wH8HNVv5yZrXrr7+w8fY6PdDW82svqKylOlk/y1wrH8KSkktLIYzF9KrkwPs/RGz1AOX pegQ== X-Gm-Message-State: AHPjjUjI+mqKATVZzh/VXpVhkWqgIKUdBiXEZvO3uiPdTsN51+I3kkJ+ zABuWtWskgZl/fusUJvRhGVGRg== X-Google-Smtp-Source: AOwi7QCz/FP7JNTOCKyHsZ646m+b2sFIQ4y0ga625MRsiFY5M58jSdmhOqbtE1aGirlry1/PMcn4ew== X-Received: by 10.101.78.201 with SMTP id w9mr5520028pgq.24.1505992045862; Thu, 21 Sep 2017 04:07:25 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id x124sm2090762pfx.56.2017.09.21.04.07.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 21 Sep 2017 04:07:24 -0700 (PDT) From: Heyi Guo To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Thu, 21 Sep 2017 18:59:52 +0800 Message-Id: <1505991597-52989-14-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1505991597-52989-1-git-send-email-heyi.guo@linaro.org> References: <1505991597-52989-1-git-send-email-heyi.guo@linaro.org> Subject: [edk2] [PATCH edk2-platforms v3 07/11] D05/PCIe: Modify PcieRegionBase of secondary chip X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, ard.biesheuvel@linaro.org, zhangjinsong2@huawei.com, guoheyi@huawei.com, waip23@126.com, wanghuiqiang@huawei.com MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" From: huangming On D05 PCIe now, 2p NA PCIe2 and 2p NB PCIe0's pci domain addresses are 0x20000000 and 0x30000000 based. These addresses overlap with the DDR memory range 0-1G. In this situation, on the inbound direction, our pcie will drop the DDR address access that are located in the pci range window and lead to a dataflow error. Modify 2p NA PCIe2 and 2p NB PCIe0's pci domain addresses to 0x40000000 and decrease PciRegion Size accordingly. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang --- Platform/Hisilicon/D05/D05.dsc | 12 ++++++------ Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl | 8 ++++---- 2 files changed, 10 insertions(+), 10 deletions(-) -- 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Leif Lindholm diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc index 01defe0..64101a7 100644 --- a/Platform/Hisilicon/D05/D05.dsc +++ b/Platform/Hisilicon/D05/D05.dsc @@ -329,12 +329,12 @@ gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize|0xbf0000 gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionBaseAddress|0x400a9400000 gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize|0xbf0000 - gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress|0x20000000 - gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize|0xd0000000 + gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress|0x40000000 + gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize|0xb0000000 gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionBaseAddress|0x400ab400000 gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize|0xbf0000 - gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress|0x30000000 - gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize|0xc0000000 + gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress|0x40000000 + gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize|0xb0000000 gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionBaseAddress|0x40000000 gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize|0xb0000000 gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionBaseAddress|0x408aa400000 @@ -352,9 +352,9 @@ gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase|0x8B9800000 gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase|0x400A8400000 gHisiTokenSpaceGuid.PcdHb1Rb1CpuMemRegionBase|0x400A9400000 - gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase|0x65020000000 + gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase|0x65040000000 gHisiTokenSpaceGuid.PcdHb1Rb3CpuMemRegionBase|0x400AB400000 - gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase|0x75030000000 + gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase|0x75040000000 gHisiTokenSpaceGuid.PcdHb1Rb5CpuMemRegionBase|0x79040000000 gHisiTokenSpaceGuid.PcdHb1Rb6CpuMemRegionBase|0x408AA400000 gHisiTokenSpaceGuid.PcdHb1Rb7CpuMemRegionBase|0x408AB400000 diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl index 79267e5..55c7f50 100644 --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl +++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl @@ -646,10 +646,10 @@ Scope(_SB) Cacheable, ReadWrite, 0x0, // Granularity - 0x20000000, // Min Base Address + 0x40000000, // Min Base Address 0xefffffff, // Max Base Address 0x65000000000, // Translate - 0xd0000000 // Length + 0xb0000000 // Length ) QWordIO ( ResourceProducer, @@ -766,10 +766,10 @@ Scope(_SB) Cacheable, ReadWrite, 0x0, // Granularity - 0x30000000, // Min Base Address + 0x40000000, // Min Base Address 0xefffffff, // Max Base Address 0x75000000000, // Translate - 0xc0000000 // Length + 0xb0000000 // Length ) QWordIO ( ResourceProducer,