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[198.145.21.10]) by mx.google.com with ESMTPS id 27si846835pfr.408.2017.09.21.04.07.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 21 Sep 2017 04:07:32 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=iVavPawm; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 3910521E87986; Thu, 21 Sep 2017 04:04:15 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received: from mail-pg0-x233.google.com (mail-pg0-x233.google.com [IPv6:2607:f8b0:400e:c05::233]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id DE3A421E1B76D for ; Thu, 21 Sep 2017 04:04:13 -0700 (PDT) Received: by mail-pg0-x233.google.com with SMTP id i195so3328856pgd.9 for ; Thu, 21 Sep 2017 04:07:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=HOf4gXBHFv49ZHuvCcZzcipUFOz3WDDuIe87W5fJkZE=; b=iVavPawmMi4mFm2YR5NNwEgPinsgWhBnBEkCOCqmj4G5ANYpuux5iahIlxezJEVozM B2CqPz1X8dJgwdHB6zCLe3Q24r186WeNHAmaPS1JUXy+RzZwWVCHv+0A4yyhWo510xz7 gmI5LSyDQMTzSEMNZJosTzdu+SMT1F53mGzxM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=HOf4gXBHFv49ZHuvCcZzcipUFOz3WDDuIe87W5fJkZE=; b=fIEiCBYGwNzt+3JgqhPZl3Gau74QFn2xY+bYPZIiQ6ZhjAf/Bso1iFf7NtJZoFUNP2 6e87+b4Vt+QNQsvLwt5EkFvivY4xN/6BpVc5e+7HcGU3hkNUdCzkxPtB9iQZTN7kLYKt rRlFd7vlsSXrVdg9INIpHceJVdbIwpEYaubAh/AOHNJbxonuxaMJJfJzNYHSh5WDrVnB eGGb10v6vhBPaudHiLQjl7sR9n9Hta0MoDlGWgiLurH469E0PxjMn60IKhmKelJaxZJr ltY7scWGe6cDMuZ06l8z18vOgrYtGpUTaGy3Aixl9U6qvaOOo2b1uOSzi0lMgNmD8/Es YnQw== X-Gm-Message-State: AHPjjUjFaLBKPpsnZOIfzw7gJ8OIo/s3rYgPCnkIkLFcX3u6sHsx/7K1 qCnBRD8HzpWF5mqUznkyQeFBXg== X-Google-Smtp-Source: AOwi7QDM0mz6WBckqca+vrP+LiUh5MMhSzKvFmGY35CxezLKCQKtwmvb4M2EcJPKRywAWHkj1mmRCw== X-Received: by 10.99.109.202 with SMTP id i193mr5260056pgc.399.1505992040359; Thu, 21 Sep 2017 04:07:20 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id x124sm2090762pfx.56.2017.09.21.04.07.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 21 Sep 2017 04:07:19 -0700 (PDT) From: Heyi Guo To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Thu, 21 Sep 2017 18:59:50 +0800 Message-Id: <1505991597-52989-12-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1505991597-52989-1-git-send-email-heyi.guo@linaro.org> References: <1505991597-52989-1-git-send-email-heyi.guo@linaro.org> Subject: [edk2] [PATCH edk2-platforms v3 06/11] Hisilicon/D05/Pcie: fix bug of size definition X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, ard.biesheuvel@linaro.org, zhangjinsong2@huawei.com, guoheyi@huawei.com, waip23@126.com, wanghuiqiang@huawei.com MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" From: huangming Fix bug of PcieRegion size definition and IO size definition. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang --- Platform/Hisilicon/D05/D05.dsc | 64 ++++++++++---------- 1 file changed, 32 insertions(+), 32 deletions(-) -- 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Leif Lindholm diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc index aa61c0e..01defe0 100644 --- a/Platform/Hisilicon/D05/D05.dsc +++ b/Platform/Hisilicon/D05/D05.dsc @@ -310,37 +310,37 @@ gHisiTokenSpaceGuid.PciHb1Rb7Base|0x700a00b0000 gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionBaseAddress|0xa8400000 - gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize|0xbeffff + gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize|0xbf0000 gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress|0xa9400000 - gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize|0xbeffff + gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize|0xbf0000 gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress|0xa8800000 - gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize|0x77effff + gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize|0x77f0000 gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionBaseAddress|0xab400000 - gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize|0xbeffff + gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize|0xbf0000 gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionBaseAddress|0xa9000000 - gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize|0x2feffff + gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize|0x2ff0000 gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress|0xb0800000 - gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize|0x77effff + gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize|0x77f0000 gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionBaseAddress|0xac900000 - gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize|0x36effff + gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize|0x36f0000 gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionBaseAddress|0xb9800000 - gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionSize|0x67effff + gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionSize|0x67f0000 gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionBaseAddress|0x400a8400000 - gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize|0xbeffff + gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize|0xbf0000 gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionBaseAddress|0x400a9400000 - gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize|0xbeffff + gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize|0xbf0000 gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress|0x20000000 - gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize|0xcfffffff + gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize|0xd0000000 gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionBaseAddress|0x400ab400000 - gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize|0xbeffff + gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize|0xbf0000 gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress|0x30000000 - gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize|0xbfffffff + gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize|0xc0000000 gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionBaseAddress|0x40000000 - gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize|0xafffffff + gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize|0xb0000000 gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionBaseAddress|0x408aa400000 - gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionSize|0xbeffff + gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionSize|0xbf0000 gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionBaseAddress|0x408ab400000 - gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionSize|0xbeffff + gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionSize|0xbf0000 gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase|0xA8400000 gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase|0xA9400000 @@ -377,52 +377,52 @@ gHisiTokenSpaceGuid.PcdHb1Rb7CpuIoRegionBase|0x408abff0000 gHisiTokenSpaceGuid.PcdHb0Rb0IoBase|0 - gHisiTokenSpaceGuid.PcdHb0Rb0IoSize|0xffff #64K + gHisiTokenSpaceGuid.PcdHb0Rb0IoSize|0x10000 #64K gHisiTokenSpaceGuid.PcdHb0Rb1IoBase|0 - gHisiTokenSpaceGuid.PcdHb0Rb1IoSize|0xffff #64K + gHisiTokenSpaceGuid.PcdHb0Rb1IoSize|0x10000 #64K gHisiTokenSpaceGuid.PcdHb0Rb2IoBase|0 - gHisiTokenSpaceGuid.PcdHb0Rb2IoSize|0xffff #64K + gHisiTokenSpaceGuid.PcdHb0Rb2IoSize|0x10000 #64K gHisiTokenSpaceGuid.PcdHb0Rb3IoBase|0 - gHisiTokenSpaceGuid.PcdHb0Rb3IoSize|0xffff #64K + gHisiTokenSpaceGuid.PcdHb0Rb3IoSize|0x10000 #64K gHisiTokenSpaceGuid.PcdHb0Rb4IoBase|0 - gHisiTokenSpaceGuid.PcdHb0Rb4IoSize|0xffff #64K + gHisiTokenSpaceGuid.PcdHb0Rb4IoSize|0x10000 #64K gHisiTokenSpaceGuid.PcdHb0Rb5IoBase|0 - gHisiTokenSpaceGuid.PcdHb0Rb5IoSize|0xffff #64K + gHisiTokenSpaceGuid.PcdHb0Rb5IoSize|0x10000 #64K gHisiTokenSpaceGuid.PcdHb0Rb6IoBase|0 - gHisiTokenSpaceGuid.PcdHb0Rb6IoSize|0xffff #64K + gHisiTokenSpaceGuid.PcdHb0Rb6IoSize|0x10000 #64K gHisiTokenSpaceGuid.PcdHb0Rb7IoBase|0 - gHisiTokenSpaceGuid.PcdHb0Rb7IoSize|0xffff #64K + gHisiTokenSpaceGuid.PcdHb0Rb7IoSize|0x10000 #64K gHisiTokenSpaceGuid.PcdHb1Rb0IoBase|0 - gHisiTokenSpaceGuid.PcdHb1Rb0IoSize|0xffff #64K + gHisiTokenSpaceGuid.PcdHb1Rb0IoSize|0x10000 #64K gHisiTokenSpaceGuid.PcdHb1Rb1IoBase|0 - gHisiTokenSpaceGuid.PcdHb1Rb1IoSize|0xffff #64K + gHisiTokenSpaceGuid.PcdHb1Rb1IoSize|0x10000 #64K gHisiTokenSpaceGuid.PcdHb1Rb2IoBase|0 - gHisiTokenSpaceGuid.PcdHb1Rb2IoSize|0xffff #64K + gHisiTokenSpaceGuid.PcdHb1Rb2IoSize|0x10000 #64K gHisiTokenSpaceGuid.PcdHb1Rb3IoBase|0 - gHisiTokenSpaceGuid.PcdHb1Rb3IoSize|0xffff #64K + gHisiTokenSpaceGuid.PcdHb1Rb3IoSize|0x10000 #64K gHisiTokenSpaceGuid.PcdHb1Rb4IoBase|0 - gHisiTokenSpaceGuid.PcdHb1Rb4IoSize|0xffff #64K + gHisiTokenSpaceGuid.PcdHb1Rb4IoSize|0x10000 #64K gHisiTokenSpaceGuid.PcdHb1Rb5IoBase|0 - gHisiTokenSpaceGuid.PcdHb1Rb5IoSize|0xffff #64K + gHisiTokenSpaceGuid.PcdHb1Rb5IoSize|0x10000 #64K gHisiTokenSpaceGuid.PcdHb1Rb6IoBase|0 - gHisiTokenSpaceGuid.PcdHb1Rb6IoSize|0xffff #64K + gHisiTokenSpaceGuid.PcdHb1Rb6IoSize|0x10000 #64K gHisiTokenSpaceGuid.PcdHb1Rb7IoBase|0 - gHisiTokenSpaceGuid.PcdHb1Rb7IoSize|0xffff #64K + gHisiTokenSpaceGuid.PcdHb1Rb7IoSize|0x10000 #64K gHisiTokenSpaceGuid.Pcdsoctype|0x1610