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[2001:19d0:306:5::1]) by mx.google.com with ESMTPS id m19si1821458pfj.277.2017.07.07.02.18.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 07 Jul 2017 02:18:58 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.b=iWHQCsvR; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 26C3721CC5374; Fri, 7 Jul 2017 02:17:16 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received: from mail-pg0-x230.google.com (mail-pg0-x230.google.com [IPv6:2607:f8b0:400e:c05::230]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 6AAFE21BADACE for ; Fri, 7 Jul 2017 02:17:15 -0700 (PDT) Received: by mail-pg0-x230.google.com with SMTP id u62so14428070pgb.3 for ; Fri, 07 Jul 2017 02:18:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=jRlva0fa4ZfP6SAHk0S0VySkEfBjTeWXAgQM0xMYCEU=; b=iWHQCsvRKmh9vcO/tbigTYbzvn9vD0kEeWGEbXoq82wUDRYhnuQc4v6W7iXxP9d/QY 4VM+mq+Qvvw4MCDQDwQT2AFSJgqFBCz7YGOoCcp/6r4sR89y446e3/XJ7UH3Is4ENFG7 A8aF6IBKQy0V0B8KrTFbKdhz34vn9/gsJRTeA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=jRlva0fa4ZfP6SAHk0S0VySkEfBjTeWXAgQM0xMYCEU=; b=Qxi8vK0qVE+Oiyk0uHHm5oSX7oCgK0cIo4t0/TwkJCHMaYt+OVmMbyzfQRsGFqRqhI TcQhpJEJgoR3NMxmFM6gCshUCxFRcrKiNlceOBTI7mhK+VYZ9STun2wvZnw2eoGGAK+v TegukAZq13lebQEhmfl4OIaQjWy6HIQDymKuR97KKnizvmVKraCOuJdjjl/+Fn+DrAkj 3PncdkfqixU7ceo8SOezH0jX4z12fMBQhhbf78jt9gw8zON61NDinn1kKePZpFk+CTy+ 1L1qoynda3xC2IPPHTYIs67ODJi/ZkCSDQ8IxHeE8GRHI5vZAl6SBK5mAHaq+Wis+TlP dXSA== X-Gm-Message-State: AIVw112SNo9b2MRUTDvpDcbzhX1dR44F+sBSKA+q4vdK3wus2Od3vGrY jOuLPBusbs8cmYhK X-Received: by 10.99.129.200 with SMTP id t191mr479795pgd.70.1499419136631; Fri, 07 Jul 2017 02:18:56 -0700 (PDT) Received: from localhost.localdomain ([113.53.228.78]) by smtp.gmail.com with ESMTPSA id s88sm5740729pfk.16.2017.07.07.02.18.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 07 Jul 2017 02:18:56 -0700 (PDT) From: Jun Nie To: leif.lindholm@linaro.org, edk2-devel@lists.01.org, evan.lloyd@arm.com, Alexei.Fedorov@arm.com, ard.biesheuvel@linaro.org Date: Fri, 7 Jul 2017 17:18:45 +0800 Message-Id: <1499419125-18297-1-git-send-email-jun.nie@linaro.org> X-Mailer: git-send-email 1.9.1 Subject: [edk2] [PATCH v3] ArmPlatformPkg: Support different PL011 reg offset X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jason.liu@linaro.org, shawn.guo@linaro.org MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" ZTE/SanChip version pl011 has different reg offset and bit offset for some registers. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jun Nie --- ArmPlatformPkg/ArmPlatformPkg.dec | 1 + ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.inf | 1 + ArmPlatformPkg/Include/Drivers/PL011Uart.h | 31 ++++++++++++++++++++++++++ 3 files changed, 33 insertions(+) -- 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Leif Lindholm diff --git a/ArmPlatformPkg/ArmPlatformPkg.dec b/ArmPlatformPkg/ArmPlatformPkg.dec index d756fd2..b8a6b13 100644 --- a/ArmPlatformPkg/ArmPlatformPkg.dec +++ b/ArmPlatformPkg/ArmPlatformPkg.dec @@ -97,6 +97,7 @@ gArmPlatformTokenSpaceGuid.PL011UartInteger|0|UINT32|0x00000020 gArmPlatformTokenSpaceGuid.PL011UartFractional|0|UINT32|0x0000002D gArmPlatformTokenSpaceGuid.PL011UartInterrupt|0x00000000|UINT32|0x0000002F + gArmPlatformTokenSpaceGuid.PL011UartRegOffsetVariant|0|UINT8|0x0000003E ## PL011 Serial Debug UART gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase|0x00000000|UINT64|0x00000030 diff --git a/ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.inf b/ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.inf index 0154f3b..3fd4602 100644 --- a/ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.inf +++ b/ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.inf @@ -39,3 +39,4 @@ gArmPlatformTokenSpaceGuid.PL011UartInteger gArmPlatformTokenSpaceGuid.PL011UartFractional + gArmPlatformTokenSpaceGuid.PL011UartRegOffsetVariant diff --git a/ArmPlatformPkg/Include/Drivers/PL011Uart.h b/ArmPlatformPkg/Include/Drivers/PL011Uart.h index d5e88e8..4957dbf 100644 --- a/ArmPlatformPkg/Include/Drivers/PL011Uart.h +++ b/ArmPlatformPkg/Include/Drivers/PL011Uart.h @@ -18,7 +18,25 @@ #include #include +#define PL011_VARIANT_ZTE 1 + // PL011 Registers +#if FixedPcdGet8 (PL011UartRegOffsetVariant) == PL011_VARIANT_ZTE +#define UARTDR 0x004 +#define UARTRSR 0x010 +#define UARTECR 0x010 +#define UARTFR 0x014 +#define UARTIBRD 0x024 +#define UARTFBRD 0x028 +#define UARTLCR_H 0x030 +#define UARTCR 0x034 +#define UARTIFLS 0x038 +#define UARTIMSC 0x040 +#define UARTRIS 0x044 +#define UARTMIS 0x048 +#define UARTICR 0x04c +#define UARTDMACR 0x050 +#else #define UARTDR 0x000 #define UARTRSR 0x004 #define UARTECR 0x004 @@ -34,6 +52,7 @@ #define UARTMIS 0x040 #define UARTICR 0x044 #define UARTDMACR 0x048 +#endif #define UARTPID0 0xFE0 #define UARTPID1 0xFE4 @@ -47,6 +66,17 @@ #define UART_STATUS_ERROR_MASK 0x0F // Flag reg bits +#if FixedPcdGet8 (PL011UartRegOffsetVariant) == PL011_VARIANT_ZTE +#define PL011_UARTFR_RI (1 << 0) // Ring indicator +#define PL011_UARTFR_TXFE (1 << 7) // Transmit FIFO empty +#define PL011_UARTFR_RXFF (1 << 6) // Receive FIFO full +#define PL011_UARTFR_TXFF (1 << 5) // Transmit FIFO full +#define PL011_UARTFR_RXFE (1 << 4) // Receive FIFO empty +#define PL011_UARTFR_BUSY (1 << 8) // UART busy +#define PL011_UARTFR_DCD (1 << 2) // Data carrier detect +#define PL011_UARTFR_DSR (1 << 3) // Data set ready +#define PL011_UARTFR_CTS (1 << 1) // Clear to send +#else #define PL011_UARTFR_RI (1 << 8) // Ring indicator #define PL011_UARTFR_TXFE (1 << 7) // Transmit FIFO empty #define PL011_UARTFR_RXFF (1 << 6) // Receive FIFO full @@ -56,6 +86,7 @@ #define PL011_UARTFR_DCD (1 << 2) // Data carrier detect #define PL011_UARTFR_DSR (1 << 1) // Data set ready #define PL011_UARTFR_CTS (1 << 0) // Clear to send +#endif // Flag reg bits - alternative names #define UART_TX_EMPTY_FLAG_MASK PL011_UARTFR_TXFE