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[118.163.176.124]) by smtp.gmail.com with ESMTPSA id y28sm16305915pfd.32.2017.06.11.19.18.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 11 Jun 2017 19:18:13 -0700 (PDT) From: Jun Nie To: ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, olivier.martin@arm.com, haojian.zhuang@linaro.org, edk2-devel@lists.01.org Date: Mon, 12 Jun 2017 10:18:05 +0800 Message-Id: <1497233885-11082-1-git-send-email-jun.nie@linaro.org> X-Mailer: git-send-email 1.9.1 Subject: [edk2] [PATCH v2] EmbeddedPkg/MmcDxe: Add non-DDR timing mode support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jason.liu@linaro.org, shawn.guo@linaro.org MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Only DDR mode is support for 8bit mode currently. Add non-DDR case when configuring ECSD. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jun Nie --- EmbeddedPkg/Universal/MmcDxe/MmcIdentification.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) -- 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Leif Lindholm diff --git a/EmbeddedPkg/Universal/MmcDxe/MmcIdentification.c b/EmbeddedPkg/Universal/MmcDxe/MmcIdentification.c index 574a77e..4ce0ddd 100644 --- a/EmbeddedPkg/Universal/MmcDxe/MmcIdentification.c +++ b/EmbeddedPkg/Universal/MmcDxe/MmcIdentification.c @@ -254,7 +254,7 @@ InitializeEmmcDevice ( EFI_MMC_HOST_PROTOCOL *Host; EFI_STATUS Status = EFI_SUCCESS; ECSD *ECSDData; - UINT32 BusClockFreq, Idx; + UINT32 BusClockFreq, Idx, BusMode; UINT32 TimingMode[4] = {EMMCHS52DDR1V2, EMMCHS52DDR1V8, EMMCHS52, EMMCHS26}; Host = MmcHostInstance->MmcHost; @@ -286,7 +286,19 @@ InitializeEmmcDevice ( } Status = Host->SetIos (Host, BusClockFreq, 8, TimingMode[Idx]); if (!EFI_ERROR (Status)) { - Status = EmmcSetEXTCSD (MmcHostInstance, EXTCSD_BUS_WIDTH, EMMC_BUS_WIDTH_DDR_8BIT); + switch (TimingMode[Idx]) { + case EMMCHS52DDR1V2: + case EMMCHS52DDR1V8: + BusMode = EMMC_BUS_WIDTH_DDR_8BIT; + break; + case EMMCHS52: + case EMMCHS26: + BusMode = EMMC_BUS_WIDTH_8BIT; + break; + default: + return EFI_UNSUPPORTED; + } + Status = EmmcSetEXTCSD (MmcHostInstance, EXTCSD_BUS_WIDTH, BusMode); if (EFI_ERROR (Status)) { DEBUG ((DEBUG_ERROR, "InitializeEmmcDevice(): Failed to set EXTCSD bus width, Status:%r\n", Status)); }