From patchwork Mon Oct 31 18:13:06 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 80250 Delivered-To: patch@linaro.org Received: by 10.80.142.83 with SMTP id 19csp270691edx; Mon, 31 Oct 2016 11:13:20 -0700 (PDT) X-Received: by 10.99.110.14 with SMTP id j14mr42841582pgc.135.1477937600426; Mon, 31 Oct 2016 11:13:20 -0700 (PDT) Return-Path: Received: from ml01.01.org (ml01.01.org. [2001:19d0:306:5::1]) by mx.google.com with ESMTPS id p185si25909865pfb.132.2016.10.31.11.13.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 31 Oct 2016 11:13:20 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id CED4081D18; Mon, 31 Oct 2016 11:13:18 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received: from mail-wm0-x236.google.com (mail-wm0-x236.google.com [IPv6:2a00:1450:400c:c09::236]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id A898D81CE2 for ; Mon, 31 Oct 2016 11:13:16 -0700 (PDT) Received: by mail-wm0-x236.google.com with SMTP id t79so65743035wmt.0 for ; Mon, 31 Oct 2016 11:13:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+KZOdS6dA/Yx5+rzrSkpbVjpvDm8EA9ipCJ5LgK9Gqg=; b=DYEq9COEpLhl3lRhf2ch3a+vxaMIYw0hKwrafur2jT372Q5cqFy7bmTuCT97D42mn/ aSJ07+z8fHhMaZ/HkxqAt1AUPRyj2DQjUvP++hXjwYRFsQ3ZD+l54BFWov8y0Uom1wpE sOLerxxeOsFjGDcTjSFQJPwNaSgp2S32dnWuE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+KZOdS6dA/Yx5+rzrSkpbVjpvDm8EA9ipCJ5LgK9Gqg=; b=Y5OJieo9MB+u5TZl6cRejyGnKuFkHMSyZvH93aFx0xN8tkWCdSBTPNnrlq/jva+FUe +jiBfGPq1b7qXL3Olv/KrAIT3vPhZdNLwkwiEToXXhk/c7kgadxxL03//0tAn9Qh8aqX eXjAl/H/xG73lx3mL7UlwC4H/FKmfaKneDq6foYY0/13KWwgoB+RPz4QoHI2x5WwljqI 3gek77gO37Vbw1CoCMSPtj+RNx+xWRwTCsf0Uh1/QnYDht8vCFncY3GJkm/PRS75m952 I4enRdnSkk92yQrc5tLDgAAt0c4CjDBO3ZNLEQJOvcvfGqRAMjne4QGjFUQHJfuuXB94 v96A== X-Gm-Message-State: ABUngvcR1xUUYMnTbgdz8WjCQBxKC9FRlwgsURSoxFyyZLVLuSzxxXWO6D4yQ8PEHQc0NLvf X-Received: by 10.28.20.73 with SMTP id 70mr10960109wmu.20.1477937596423; Mon, 31 Oct 2016 11:13:16 -0700 (PDT) Received: from localhost.localdomain ([105.151.153.127]) by smtp.gmail.com with ESMTPSA id 132sm26054809wmn.16.2016.10.31.11.13.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 31 Oct 2016 11:13:15 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org Date: Mon, 31 Oct 2016 18:13:06 +0000 Message-Id: <1477937590-10361-2-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1477937590-10361-1-git-send-email-ard.biesheuvel@linaro.org> References: <1477937590-10361-1-git-send-email-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH 1/5] EmbeddedPkg: introduce platform PCI I/O protocol X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Introduce a protocol that can be exposed by a platform for devices that can be driven by a PCI driver, (e.g., AHCI, XHCI), but do not live on a PCI bus. This used to be called 'PCI emulation' but given that we only emulate the PCI config space and nothing else, it tends to be a bit confusing so this introduces the term 'platform PCI I/O' instead. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel --- EmbeddedPkg/EmbeddedPkg.dec | 1 + EmbeddedPkg/Include/Protocol/PlatformPciIo.h | 74 ++++++++++++++++++++ 2 files changed, 75 insertions(+) -- 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/EmbeddedPkg/EmbeddedPkg.dec b/EmbeddedPkg/EmbeddedPkg.dec index 2c2cf41103c2..84a6f4d01077 100644 --- a/EmbeddedPkg/EmbeddedPkg.dec +++ b/EmbeddedPkg/EmbeddedPkg.dec @@ -69,6 +69,7 @@ [Protocols.common] gAndroidFastbootPlatformProtocolGuid = { 0x524685a0, 0x89a0, 0x11e3, {0x9d, 0x4d, 0xbf, 0xa9, 0xf6, 0xa4, 0x03, 0x08}} gUsbDeviceProtocolGuid = { 0x021bd2ca, 0x51d2, 0x11e3, {0x8e, 0x56, 0xb7, 0x54, 0x17, 0xc7, 0x0b, 0x44 }} gPlatformGpioProtocolGuid = { 0x52ce9845, 0x5af4, 0x43e2, {0xba, 0xfd, 0x23, 0x08, 0x12, 0x54, 0x7a, 0xc2 }} + gPlatformPciIoProtocolGuid = { 0x0d51905b, 0xb77e, 0x452a, {0xa2, 0xc0, 0xec, 0xa0, 0xcc, 0x8d, 0x51, 0x4a }} [PcdsFeatureFlag.common] gEmbeddedTokenSpaceGuid.PcdEmbeddedMacBoot|FALSE|BOOLEAN|0x00000001 diff --git a/EmbeddedPkg/Include/Protocol/PlatformPciIo.h b/EmbeddedPkg/Include/Protocol/PlatformPciIo.h new file mode 100644 index 000000000000..a7bd584049ac --- /dev/null +++ b/EmbeddedPkg/Include/Protocol/PlatformPciIo.h @@ -0,0 +1,74 @@ +/** @file + + Copyright (c) 2016, Linaro, Ltd. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __PLATFORM_PCI_IO_H__ +#define __PLATFORM_PCI_IO_H__ + +#define PLATFORM_PCI_IO_PROTOCOL_GUID \ + { 0x0d51905b, 0xb77e, 0x452a, {0xa2, 0xc0, 0xec, 0xa0, 0xcc, 0x8d, 0x51, 0x4a } } + +// +// Protocol interface structure +// +typedef struct _PLATFORM_PCI_IO PLATFORM_PCI_IO; + +// +// Data Types +// +typedef enum { + PlatformPciIoDeviceOhci, + PlatformPciIoDeviceUhci, + PlatformPciIoDeviceEhci, + PlatformPciIoDeviceXhci, + PlatformPciIoDeviceAhci, + PlatformPciIoDeviceMax, +} PLATFORM_PCI_IO_DEVICE_TYPE; + +typedef enum { + PlatformPciIoDmaCoherent, + PlatformPciIoDmaNonCoherent, + PlatformPciIoDmaMax, +} PLATFORM_PCI_IO_DMA_TYPE; + +// +// Function Prototypes +// +typedef +EFI_STATUS +(EFIAPI *PLATFORM_PCI_IO_INIT) ( + IN PLATFORM_PCI_IO *This + ); + +struct _PLATFORM_PCI_IO { + // + // The MMIO address of the device + // + EFI_PHYSICAL_ADDRESS BaseAddress; + // + // The type of device + // + PLATFORM_PCI_IO_DEVICE_TYPE DeviceType; + // + // Whether this device is DMA coherent + // + PLATFORM_PCI_IO_DMA_TYPE DmaType; + // + // Initialization function for the device + // + PLATFORM_PCI_IO_INIT Initialize; +}; + +extern EFI_GUID gPlatformPciIoProtocolGuid; + +#endif