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[198.145.21.10]) by mx.google.com with ESMTPS id to7si28339874pac.282.2016.09.05.02.17.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 05 Sep 2016 02:17:51 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 496561A1E31; Mon, 5 Sep 2016 02:17:50 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received: from mail-wm0-x229.google.com (mail-wm0-x229.google.com [IPv6:2a00:1450:400c:c09::229]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 005501A1E30 for ; Mon, 5 Sep 2016 02:17:48 -0700 (PDT) Received: by mail-wm0-x229.google.com with SMTP id w2so112579600wmd.0 for ; Mon, 05 Sep 2016 02:17:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=2LD/2ndL3agts5XR7MIGmQsThPxj4cX2fYk9SBHdxcg=; b=Th+57xrFRPo9JA3ZiLTm/iZd8B+tt2IUbl3mQ6PDnGo7CFy9MTPCEYNeEgRHPWv+WD i+sU0/ORzKLc5/DMgp3pPLRCwcOTvOUpN1lwCEEB2Kg5JmjODHK4mjeiwWfqnYaAb36m sMLbF1CO1+uMngqTYWSv6IkSommggQApblfu0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=2LD/2ndL3agts5XR7MIGmQsThPxj4cX2fYk9SBHdxcg=; b=RTBMjaSK+6BIoMR7MKQ5Y5GScGjDBUF7u1cjwtbsbW+5GhBuTSOWrKvlnN917IVQ7g UjgiSttegULC3NjWQxV8u5MS4iYSq3lwr1S5wqXvIXuGdL32pAD8lvc7tpIxhHnGfimE Do+9DXaE+ysBLY7qmmuWyNCLtMGMSAuVxntft7sKEsiHk7AB2sYwe5A3NRaOIf+VtZoR BFuznHZvrkoIhvm6nThlr8XffmM3lEvYeOaNmpEYl1DL9FgQaR787lj1+KE7NZE9ISRh zl2vVYAiuyW/QmF59jowkTXaABv3uSTYhCNs+x+nBcQGJ2ZqDobHxr5p+6q9zm0TeIid pI5A== X-Gm-Message-State: AE9vXwMeJKe2HnqfFS8neKAGVnYHABbBA0F6Qi3UksRHUunKLLRIuUUzRhjQ+m/tqzxrEe3w X-Received: by 10.28.199.65 with SMTP id x62mr4179842wmf.106.1473067067560; Mon, 05 Sep 2016 02:17:47 -0700 (PDT) Received: from localhost.localdomain ([197.130.133.164]) by smtp.gmail.com with ESMTPSA id m133sm10157457wmg.0.2016.09.05.02.17.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Sep 2016 02:17:46 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org, feng.tian@intel.com, star.zeng@intel.com, liming.gao@intel.com Date: Mon, 5 Sep 2016 10:17:24 +0100 Message-Id: <1473067049-16252-3-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1473067049-16252-1-git-send-email-ard.biesheuvel@linaro.org> References: <1473067049-16252-1-git-send-email-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH 2/7] MdeModulePkg/EhciDxe: enable 64-bit PCI DMA X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lersek@redhat.com, leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" PCI controller drivers must set the EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE attribute if the controller supports 64-bit DMA addressing. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel --- MdeModulePkg/Bus/Pci/EhciDxe/Ehci.c | 22 +++++++++++++++++++- MdeModulePkg/Bus/Pci/EhciDxe/Ehci.h | 2 ++ MdeModulePkg/Bus/Pci/EhciDxe/EhciSched.c | 2 +- 3 files changed, 24 insertions(+), 2 deletions(-) -- 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Laszlo Ersek diff --git a/MdeModulePkg/Bus/Pci/EhciDxe/Ehci.c b/MdeModulePkg/Bus/Pci/EhciDxe/Ehci.c index 4e9e05f0e431..e4c7e59526de 100644 --- a/MdeModulePkg/Bus/Pci/EhciDxe/Ehci.c +++ b/MdeModulePkg/Bus/Pci/EhciDxe/Ehci.c @@ -89,7 +89,7 @@ EhcGetCapability ( *MaxSpeed = EFI_USB_SPEED_HIGH; *PortNumber = (UINT8) (Ehc->HcStructParams & HCSP_NPORTS); - *Is64BitCapable = (UINT8) (Ehc->HcCapParams & HCCP_64BIT); + *Is64BitCapable = (UINT8) Ehc->Support64BitDma; DEBUG ((EFI_D_INFO, "EhcGetCapability: %d ports, 64 bit %d\n", *PortNumber, *Is64BitCapable)); @@ -1877,6 +1877,26 @@ EhcDriverBindingStart ( goto CLOSE_PCIIO; } + // + // Enable 64-bit DMA support in the PCI layer if this controller + // supports it. + // + if ((Ehc->HcCapParams & HCCP_64BIT) != 0) { + Status = PciIo->Attributes ( + PciIo, + EfiPciIoAttributeOperationEnable, + EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE, + NULL + ); + if (!EFI_ERROR (Status)) { + Ehc->Support64BitDma = TRUE; + } else { + DEBUG ((EFI_D_WARN, + "EhcDriverBindingStart: failed to enable 64-bit DMA on 64-bit capable controller @ %p (%r)\n", + Controller, Status)); + } + } + Status = gBS->InstallProtocolInterface ( &Controller, &gEfiUsb2HcProtocolGuid, diff --git a/MdeModulePkg/Bus/Pci/EhciDxe/Ehci.h b/MdeModulePkg/Bus/Pci/EhciDxe/Ehci.h index 7177658092c3..be81bde40d9b 100644 --- a/MdeModulePkg/Bus/Pci/EhciDxe/Ehci.h +++ b/MdeModulePkg/Bus/Pci/EhciDxe/Ehci.h @@ -173,6 +173,8 @@ struct _USB2_HC_DEV { UINT16 DebugPortOffset; // The offset of debug port mmio register UINT8 DebugPortBarNum; // The bar number of debug port mmio register UINT8 DebugPortNum; // The port number of usb debug port + + BOOLEAN Support64BitDma; // Whether 64 bit DMA may be used with this device }; diff --git a/MdeModulePkg/Bus/Pci/EhciDxe/EhciSched.c b/MdeModulePkg/Bus/Pci/EhciDxe/EhciSched.c index 5594e6699ea6..036c00b32b40 100644 --- a/MdeModulePkg/Bus/Pci/EhciDxe/EhciSched.c +++ b/MdeModulePkg/Bus/Pci/EhciDxe/EhciSched.c @@ -178,7 +178,7 @@ EhcInitSched ( // Ehc->MemPool = UsbHcInitMemPool ( PciIo, - EHC_BIT_IS_SET (Ehc->HcCapParams, HCCP_64BIT), + Ehc->Support64BitDma, EHC_HIGH_32BIT (PhyAddr) );