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[198.145.21.10]) by mx.google.com with ESMTPS id he5si360560pac.171.2016.07.07.10.23.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 07 Jul 2016 10:23:03 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 1B3FB1A1E9C; Thu, 7 Jul 2016 10:23:44 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received: from mail-wm0-x231.google.com (mail-wm0-x231.google.com [IPv6:2a00:1450:400c:c09::231]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 2FA6D1A1E5F for ; Thu, 7 Jul 2016 10:23:42 -0700 (PDT) Received: by mail-wm0-x231.google.com with SMTP id f126so219072408wma.1 for ; Thu, 07 Jul 2016 10:23:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=HovUZAQko3ngqZC1mTPF0r3U1YX63Q8bNp5/SIl9cjs=; b=G2XrdyQVesKMnldX94IgB/7hYk6tIT8z6Rujc3B1EdD05r8QuIm243MAY++h15fXKW YTnqf0sfJwHX9oJooB+ywCjsY7gfdbyw05VAxJLwBGBIIWWWIziHGCls2KWYYKQZO8kZ Td9yXPxYrkKPVs32moDtTJAhUc8oWAa3ZNlos= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=HovUZAQko3ngqZC1mTPF0r3U1YX63Q8bNp5/SIl9cjs=; b=lxjAy84sT2xQtMgUrBRt/zu6naeqstZU874zRSakZgjqK/X82h7iEIq1kj4bUkV0VN x5u7j/mIvpNfYYkiRH+GDP8Cqy8fInBqLoKHvUKHw1Q+msHB0SFuYn49klCXz7PiFyqN MhT9TsMp+AxwP5wljWjExtXobO/FYu50bDYY6saFM96q7ZaVaGye5oR01MeFLVxrtv9Q D45i6T6wie6Fq4fwYwzE1qGcpiZ7sgl6x1MNYpG6I8RdjFWrtKlv+5vtozYRckvNzpZY +HTsCbgPHJshSeZ1WeYY6KH4+0lxlSvrLMGQcfXunK1RhfEFzzy7Yb2nbG7z2yoAkSC+ 24fw== X-Gm-Message-State: ALyK8tLAbVlm/TzWNShjt8/8BWKrlAF92NGv4V8h7LHjlguIIDwSvCZoKtUX7MQa7w2pegow X-Received: by 10.28.127.198 with SMTP id a189mr1980780wmd.16.1467912179386; Thu, 07 Jul 2016 10:22:59 -0700 (PDT) Received: from localhost.localdomain ([188.203.148.129]) by smtp.gmail.com with ESMTPSA id w184sm1757077wmd.11.2016.07.07.10.22.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 07 Jul 2016 10:22:58 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org Date: Thu, 7 Jul 2016 19:22:47 +0200 Message-Id: <1467912167-4303-1-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 Subject: [edk2] [PATCH] ArmPkg/ArmGicLib: manage GICv3 SPI state at the distributor X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Unlike SGIs and PPIs, which are private to the CPU and are managed at the redistributor level (which is also a per-CPU construct), shared interrupts (SPIs) are shared between all CPUs, and therefore managed at the distributor level. Reported-by: Narinder Dhillon Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel --- ArmPkg/Drivers/ArmGic/ArmGicLib.c | 25 +++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-) -- 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Leif Lindholm diff --git a/ArmPkg/Drivers/ArmGic/ArmGicLib.c b/ArmPkg/Drivers/ArmGic/ArmGicLib.c index 248e896c4b94..73795ed4e56c 100644 --- a/ArmPkg/Drivers/ArmGic/ArmGicLib.c +++ b/ArmPkg/Drivers/ArmGic/ArmGicLib.c @@ -20,6 +20,19 @@ #include /** + * + * Return whether the Source interrupt index refers to a shared interrupt (SPI) + */ +STATIC +BOOLEAN +SourceIsSpi ( + IN UINTN Source + ) +{ + return Source >= 32 && Source < 1020; +} + +/** * Return the base address of the GIC redistributor for the current CPU * * @param Revision GIC Revision. The GIC redistributor might have a different @@ -183,7 +196,9 @@ ArmGicEnableInterrupt ( RegShift = Source % 32; Revision = ArmGicGetSupportedArchRevision (); - if ((Revision == ARM_GIC_ARCH_REVISION_2) || FeaturePcdGet (PcdArmGicV3WithV2Legacy)) { + if ((Revision == ARM_GIC_ARCH_REVISION_2) || + FeaturePcdGet (PcdArmGicV3WithV2Legacy) || + SourceIsSpi (Source)) { // Write set-enable register MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset), 1 << RegShift); } else { @@ -216,7 +231,9 @@ ArmGicDisableInterrupt ( RegShift = Source % 32; Revision = ArmGicGetSupportedArchRevision (); - if ((Revision == ARM_GIC_ARCH_REVISION_2) || FeaturePcdGet (PcdArmGicV3WithV2Legacy)) { + if ((Revision == ARM_GIC_ARCH_REVISION_2) || + FeaturePcdGet (PcdArmGicV3WithV2Legacy) || + SourceIsSpi (Source)) { // Write clear-enable register MmioWrite32 (GicDistributorBase + ARM_GIC_ICDICER + (4 * RegOffset), 1 << RegShift); } else { @@ -249,7 +266,9 @@ ArmGicIsInterruptEnabled ( RegShift = Source % 32; Revision = ArmGicGetSupportedArchRevision (); - if ((Revision == ARM_GIC_ARCH_REVISION_2) || FeaturePcdGet (PcdArmGicV3WithV2Legacy)) { + if ((Revision == ARM_GIC_ARCH_REVISION_2) || + FeaturePcdGet (PcdArmGicV3WithV2Legacy) || + SourceIsSpi (Source)) { Interrupts = ((MmioRead32 (GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset)) & (1 << RegShift)) != 0); } else { GicCpuRedistributorBase = GicGetCpuRedistributorBase (GicRedistributorBase, Revision);