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[198.145.21.10]) by mx.google.com with ESMTPS id c8si18584912pag.244.2016.04.29.08.41.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 29 Apr 2016 08:41:29 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 978401A1F76; Fri, 29 Apr 2016 08:41:28 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received: from mail-wm0-x22f.google.com (mail-wm0-x22f.google.com [IPv6:2a00:1450:400c:c09::22f]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 105C91A1F54 for ; Fri, 29 Apr 2016 08:41:27 -0700 (PDT) Received: by mail-wm0-x22f.google.com with SMTP id g17so42795943wme.1 for ; Fri, 29 Apr 2016 08:41:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=WayjCToOgvymFgXNYuSZecfdGH+eyqmm58pBoo6VFjE=; b=QHKf/MdxbTiHJDftnWrTErlw/s4BG3rFWBRnGbFaa8Mi74z3I3srD8at//KRsmRs// ZaPvEBtOw55wqiR+A7tjQtma4q8eRTkViIdDjuRbdR8TocPLol8Y93pLvElCOfOJkbm3 0HrmRUr7RzONTQ/DZyLhjo09AnqOivX+eq8Ws= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=WayjCToOgvymFgXNYuSZecfdGH+eyqmm58pBoo6VFjE=; b=ZcJaHXvue2ywtMqjAS/wsKxiSIMHUXsoctDIC7Rg7VMuHIaKG4BNBMfz9BJOMogGvb 0ckiRxJXH5r7JajRGDe44U3Evcq/Gt7QRmFBhp6ZQJlRxBqPbSqFLcNexHeut33qGDhc HzkGED16cBXknm3m+uVDuKuOa04s11NVIJX1M5bJJKNjB/UHR7SyFPwiheNtABRGE50n /CzKPOLaTzQw8KLjMXcPOoeM2KZv77OrOs+Rv34gIymQCp/1EL8S+2MXFna2kTMXfo9f EMetb12fRuHDiAzFisGPeZ0BV6qiqnS9085KxVogjvEtMcUO2CQgFqlxbP1zLbZqDPGz s/EQ== X-Gm-Message-State: AOPr4FWki2krB1h29wJCVADZA1uTZ6kSFDlydBWBZcmPbnj5sFrukgDoBXKIBbx0KrE9IYrl X-Received: by 10.194.11.36 with SMTP id n4mr24166962wjb.10.1461944485051; Fri, 29 Apr 2016 08:41:25 -0700 (PDT) Received: from localhost.localdomain ([195.55.142.58]) by smtp.gmail.com with ESMTPSA id b15sm3857721wmd.1.2016.04.29.08.41.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 29 Apr 2016 08:41:24 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org Date: Fri, 29 Apr 2016 17:41:19 +0200 Message-Id: <1461944480-8912-1-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 Subject: [edk2] [PATCH 1/2] ArmPlatformPkg: move PCI related PCD definitions to ArmPkg X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" The PCI related PCDs are not platform specific, and architectural protocols such as CpuIo2 are based on PCI provided MMIO to IO translation, so these PCDs belong in ArmPkg not ArmPlatformPkg. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel --- ArmPkg/ArmPkg.dec | 62 ++++++++++++++++++++ ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.inf | 4 +- ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf | 16 ++--- ArmPlatformPkg/ArmJunoPkg/Library/ArmJunoLib/ArmJunoLib.inf | 8 +-- ArmPlatformPkg/ArmPlatformPkg.dec | 62 -------------------- 5 files changed, 76 insertions(+), 76 deletions(-) -- 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Leif Lindholm diff --git a/ArmPkg/ArmPkg.dec b/ArmPkg/ArmPkg.dec index e90306653864..75c238aa1e3d 100644 --- a/ArmPkg/ArmPkg.dec +++ b/ArmPkg/ArmPkg.dec @@ -255,3 +255,65 @@ [PcdsFixedAtBuild.common, PcdsDynamic.common] gArmTokenSpaceGuid.PcdGicRedistributorsBase|0|UINT32|0x0000000E gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT32|0x0000000D gArmTokenSpaceGuid.PcdGicSgiIntId|0|UINT32|0x00000025 + + # + # Bases, sizes and translation offsets of IO and MMIO spaces, respectively. + # Note that "IO" is just another MMIO range that simulates IO space; there + # are no special instructions to access it. + # + # The base addresses PcdPciIoBase, PcdPciMmio32Base and PcdPciMmio64Base are + # specific to their containing address spaces. In order to get the physical + # address for the CPU, for a given access, the respective translation value + # has to be added. + # + # The translations always have to be initialized like this, using UINT64: + # + # UINT64 IoCpuBase; // mapping target in 64-bit cpu-physical space + # UINT64 Mmio32CpuBase; // mapping target in 64-bit cpu-physical space + # UINT64 Mmio64CpuBase; // mapping target in 64-bit cpu-physical space + # + # PcdPciIoTranslation = IoCpuBase - PcdPciIoBase; + # PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base; + # PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base; + # + # because (a) the target address space (ie. the cpu-physical space) is + # 64-bit, and (b) the translation values are meant as offsets for *modular* + # arithmetic. + # + # Accordingly, the translation itself needs to be implemented as: + # + # UINT64 UntranslatedIoAddress; // input parameter + # UINT32 UntranslatedMmio32Address; // input parameter + # UINT64 UntranslatedMmio64Address; // input parameter + # + # UINT64 TranslatedIoAddress; // output parameter + # UINT64 TranslatedMmio32Address; // output parameter + # UINT64 TranslatedMmio64Address; // output parameter + # + # TranslatedIoAddress = UntranslatedIoAddress + + # PcdPciIoTranslation; + # TranslatedMmio32Address = (UINT64)UntranslatedMmio32Address + + # PcdPciMmio32Translation; + # TranslatedMmio64Address = UntranslatedMmio64Address + + # PcdPciMmio64Translation; + # + # The modular arithmetic performed in UINT64 ensures that the translation + # works correctly regardless of the relation between IoCpuBase and + # PcdPciIoBase, Mmio32CpuBase and PcdPciMmio32Base, and Mmio64CpuBase and + # PcdPciMmio64Base. + # + gArmTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x00000050 + gArmTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x00000051 + gArmTokenSpaceGuid.PcdPciIoTranslation|0x0|UINT64|0x00000052 + gArmTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT32|0x00000053 + gArmTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT32|0x00000054 + gArmTokenSpaceGuid.PcdPciMmio32Translation|0x0|UINT64|0x00000055 + gArmTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x00000056 + gArmTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x00000057 + gArmTokenSpaceGuid.PcdPciMmio64Translation|0x0|UINT64|0x00000058 + + # + # Inclusive range of allowed PCI buses. + # + gArmTokenSpaceGuid.PcdPciBusMin|0x0|UINT32|0x00000059 + gArmTokenSpaceGuid.PcdPciBusMax|0x0|UINT32|0x0000005A diff --git a/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.inf b/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.inf index 6ab81e8dd60a..a2617982b259 100644 --- a/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.inf +++ b/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.inf @@ -80,8 +80,8 @@ [FixedPcd] # PCI Root complex specific PCDs gArmJunoTokenSpaceGuid.PcdPciConfigurationSpaceBaseAddress - gArmPlatformTokenSpaceGuid.PcdPciBusMin - gArmPlatformTokenSpaceGuid.PcdPciBusMax + gArmTokenSpaceGuid.PcdPciBusMin + gArmTokenSpaceGuid.PcdPciBusMax [Pcd] gEmbeddedTokenSpaceGuid.PcdFdtDevicePaths diff --git a/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf b/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf index 9f526910c48a..de28c805ae6e 100644 --- a/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf +++ b/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf @@ -58,14 +58,14 @@ [Pcd.common] gArmTokenSpaceGuid.PcdSystemMemoryBase gArmTokenSpaceGuid.PcdSystemMemorySize - gArmPlatformTokenSpaceGuid.PcdPciBusMin - gArmPlatformTokenSpaceGuid.PcdPciBusMax - gArmPlatformTokenSpaceGuid.PcdPciIoBase - gArmPlatformTokenSpaceGuid.PcdPciIoSize - gArmPlatformTokenSpaceGuid.PcdPciMmio32Base - gArmPlatformTokenSpaceGuid.PcdPciMmio32Size - gArmPlatformTokenSpaceGuid.PcdPciMmio64Base - gArmPlatformTokenSpaceGuid.PcdPciMmio64Size + gArmTokenSpaceGuid.PcdPciBusMin + gArmTokenSpaceGuid.PcdPciBusMax + gArmTokenSpaceGuid.PcdPciIoBase + gArmTokenSpaceGuid.PcdPciIoSize + gArmTokenSpaceGuid.PcdPciMmio32Base + gArmTokenSpaceGuid.PcdPciMmio32Size + gArmTokenSpaceGuid.PcdPciMmio64Base + gArmTokenSpaceGuid.PcdPciMmio64Size gArmJunoTokenSpaceGuid.PcdPcieControlBaseAddress gArmJunoTokenSpaceGuid.PcdPcieRootPortBaseAddress diff --git a/ArmPlatformPkg/ArmJunoPkg/Library/ArmJunoLib/ArmJunoLib.inf b/ArmPlatformPkg/ArmJunoPkg/Library/ArmJunoLib/ArmJunoLib.inf index 530bb1cb9dc0..8c8b141c35a2 100644 --- a/ArmPlatformPkg/ArmJunoPkg/Library/ArmJunoLib/ArmJunoLib.inf +++ b/ArmPlatformPkg/ArmJunoPkg/Library/ArmJunoLib/ArmJunoLib.inf @@ -58,10 +58,10 @@ [FixedPcd] gArmJunoTokenSpaceGuid.PcdPciConfigurationSpaceSize [Pcd] - gArmPlatformTokenSpaceGuid.PcdPciMmio32Base - gArmPlatformTokenSpaceGuid.PcdPciMmio32Size - gArmPlatformTokenSpaceGuid.PcdPciMmio64Base - gArmPlatformTokenSpaceGuid.PcdPciMmio64Size + gArmTokenSpaceGuid.PcdPciMmio32Base + gArmTokenSpaceGuid.PcdPciMmio32Size + gArmTokenSpaceGuid.PcdPciMmio64Base + gArmTokenSpaceGuid.PcdPciMmio64Size [Ppis] gArmMpCoreInfoPpiGuid diff --git a/ArmPlatformPkg/ArmPlatformPkg.dec b/ArmPlatformPkg/ArmPlatformPkg.dec index 0a7e78443eff..1c05132cd625 100644 --- a/ArmPlatformPkg/ArmPlatformPkg.dec +++ b/ArmPlatformPkg/ArmPlatformPkg.dec @@ -125,68 +125,6 @@ [PcdsFixedAtBuild.common,PcdsDynamic.common] gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x0|UINT32|0x00000024 gArmPlatformTokenSpaceGuid.PcdPL031RtcPpmAccuracy|300000000|UINT32|0x00000022 - # - # Inclusive range of allowed PCI buses. - # - gArmPlatformTokenSpaceGuid.PcdPciBusMin|0x0|UINT32|0x0000003E - gArmPlatformTokenSpaceGuid.PcdPciBusMax|0x0|UINT32|0x0000003F - - # - # Bases, sizes and translation offsets of IO and MMIO spaces, respectively. - # Note that "IO" is just another MMIO range that simulates IO space; there - # are no special instructions to access it. - # - # The base addresses PcdPciIoBase, PcdPciMmio32Base and PcdPciMmio64Base are - # specific to their containing address spaces. In order to get the physical - # address for the CPU, for a given access, the respective translation value - # has to be added. - # - # The translations always have to be initialized like this, using UINT64: - # - # UINT64 IoCpuBase; // mapping target in 64-bit cpu-physical space - # UINT64 Mmio32CpuBase; // mapping target in 64-bit cpu-physical space - # UINT64 Mmio64CpuBase; // mapping target in 64-bit cpu-physical space - # - # PcdPciIoTranslation = IoCpuBase - PcdPciIoBase; - # PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base; - # PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base; - # - # because (a) the target address space (ie. the cpu-physical space) is - # 64-bit, and (b) the translation values are meant as offsets for *modular* - # arithmetic. - # - # Accordingly, the translation itself needs to be implemented as: - # - # UINT64 UntranslatedIoAddress; // input parameter - # UINT32 UntranslatedMmio32Address; // input parameter - # UINT64 UntranslatedMmio64Address; // input parameter - # - # UINT64 TranslatedIoAddress; // output parameter - # UINT64 TranslatedMmio32Address; // output parameter - # UINT64 TranslatedMmio64Address; // output parameter - # - # TranslatedIoAddress = UntranslatedIoAddress + - # PcdPciIoTranslation; - # TranslatedMmio32Address = (UINT64)UntranslatedMmio32Address + - # PcdPciMmio32Translation; - # TranslatedMmio64Address = UntranslatedMmio64Address + - # PcdPciMmio64Translation; - # - # The modular arithmetic performed in UINT64 ensures that the translation - # works correctly regardless of the relation between IoCpuBase and - # PcdPciIoBase, Mmio32CpuBase and PcdPciMmio32Base, and Mmio64CpuBase and - # PcdPciMmio64Base. - # - gArmPlatformTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x00000040 - gArmPlatformTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x00000041 - gArmPlatformTokenSpaceGuid.PcdPciIoTranslation|0x0|UINT64|0x00000042 - gArmPlatformTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT32|0x00000043 - gArmPlatformTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT32|0x00000044 - gArmPlatformTokenSpaceGuid.PcdPciMmio32Translation|0x0|UINT64|0x00000045 - gArmPlatformTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x00000046 - gArmPlatformTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x00000047 - gArmPlatformTokenSpaceGuid.PcdPciMmio64Translation|0x0|UINT64|0x00000048 - [PcdsFixedAtBuild.ARM] # Stack for CPU Cores in Secure Monitor Mode gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT64|0x00000007