From patchwork Thu Mar 17 13:20:10 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 63991 Delivered-To: patch@linaro.org Received: by 10.112.199.169 with SMTP id jl9csp464283lbc; Thu, 17 Mar 2016 06:20:38 -0700 (PDT) X-Received: by 10.98.8.200 with SMTP id 69mr15097647pfi.39.1458220838059; Thu, 17 Mar 2016 06:20:38 -0700 (PDT) Return-Path: Received: from ml01.01.org (ml01.01.org. [198.145.21.10]) by mx.google.com with ESMTPS id 66si1162797pfl.7.2016.03.17.06.20.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 17 Mar 2016 06:20:38 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dkim=neutral (body hash did not verify) header.i=@linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 9F31B1A1E30; Thu, 17 Mar 2016 06:20:57 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received: from mail-wm0-x231.google.com (mail-wm0-x231.google.com [IPv6:2a00:1450:400c:c09::231]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 8156E1A1E39 for ; Thu, 17 Mar 2016 06:20:55 -0700 (PDT) Received: by mail-wm0-x231.google.com with SMTP id l68so116909571wml.1 for ; Thu, 17 Mar 2016 06:20:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=7YQZ+e0P9uWmiAGnPfHdp0l1dPjETf/xTi+vKsLm53o=; b=X50jLP7I6SznMT7H6JR5xVIHsNclj4gbyNfz+JWlxbXI150ollIpIBXovePX1TbQBs SP/SiXCZyer/Y2RAN8tu4o575xbRnOGiaVSjsGRtubX9JwsRKXxWPE2DCc/34bZ94Knz JeREML5WZFvcHaVQdFFO/PCZ8Xi4z0euIlDx0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7YQZ+e0P9uWmiAGnPfHdp0l1dPjETf/xTi+vKsLm53o=; b=c2rASaRJrceMbq4IkKjxtpad+u0/zgD+1AMsUpv7x+K+Z2Z02C7bdOkJgK8ofhi/au D5lrOa2QR0HjfBTonBd+HPxy/Gd3fDP1UihCj9eX42dWAImhdbsC2ZbAaE4g35t4TRef Z92fnjXoz4NTsdxyWo/+UL9zpIpKkGLtZai558CaeXQbvBn27SL9u3nxGpUpbHUgRp5D ht7N2oJaUZkgQVoV6YN6TNHrkkMEn5oppibuRVMteWF0zceCu/s7r18jAaUdBORpH61g Oevi/OF1HmzK7o2zVSXWYS2gvvaC1x70muBVYcY7iyfOJ8HEmME4MlCiOcGY4rsKHVKU Y1Vw== X-Gm-Message-State: AD7BkJKpfZwIDaw3mSLlIuSeLRzGwuHHVrDfA8Q6s7NP/dP6RkFvyO3ZWUZYx2fhcbtBvTLe X-Received: by 10.28.148.8 with SMTP id w8mr36303360wmd.90.1458220834231; Thu, 17 Mar 2016 06:20:34 -0700 (PDT) Received: from localhost.localdomain ([195.55.142.58]) by smtp.gmail.com with ESMTPSA id v5sm30198913wmg.16.2016.03.17.06.20.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 17 Mar 2016 06:20:33 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org, eugene@hp.com Date: Thu, 17 Mar 2016 14:20:10 +0100 Message-Id: <1458220815-6944-3-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1458220815-6944-1-git-send-email-ard.biesheuvel@linaro.org> References: <1458220815-6944-1-git-send-email-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH 2/7] ArmPkg/ArmExceptionLib: fold exception handler prologue into vector table X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Unlike the AArch32 vector table, which has room for a single instruction for each exception type, the AArch64 exception table has 128 byte slots, which can easily hold the shared prologues that are emitted out of line. So refactor this code into a single macro, and expand it into each vector table slot. Since the address of the command handler entry point is no longer patched in by the C code, we can just emit the literal into each vector entry directly. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel --- ArmPkg/Library/ArmExceptionLib/AArch64/ExceptionSupport.S | 112 +++++++------------- 1 file changed, 39 insertions(+), 73 deletions(-) -- 2.5.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/ArmPkg/Library/ArmExceptionLib/AArch64/ExceptionSupport.S b/ArmPkg/Library/ArmExceptionLib/AArch64/ExceptionSupport.S index 790ce009b8de..c47974b81e8b 100644 --- a/ArmPkg/Library/ArmExceptionLib/AArch64/ExceptionSupport.S +++ b/ArmPkg/Library/ArmExceptionLib/AArch64/ExceptionSupport.S @@ -99,8 +99,6 @@ */ GCC_ASM_EXPORT(ExceptionHandlersEnd) -GCC_ASM_EXPORT(CommonExceptionEntry) -GCC_ASM_EXPORT(AsmCommonExceptionEntry) GCC_ASM_EXPORT(CommonCExceptionHandler) .text @@ -172,142 +170,110 @@ ASM_PFX(ExceptionHandlersStart): VECTOR_BASE(ExceptionHandlersStart) #endif +#undef REG_PAIR +#undef REG_ONE +#define REG_PAIR(REG1, REG2, OFFSET, CONTEXT_SIZE) stp REG1, REG2, [sp, #(OFFSET-CONTEXT_SIZE)] +#define REG_ONE(REG1, OFFSET, CONTEXT_SIZE) stur REG1, [sp, #(OFFSET-CONTEXT_SIZE)] + + .macro ExceptionEntry, val + // Move the stackpointer so we can reach our structure with the str instruction. + sub sp, sp, #(FP_CONTEXT_SIZE + SYS_CONTEXT_SIZE) + + // Save all the General regs before touching x0 and x1. + // This does not save r31(SP) as it is special. We do that later. + ALL_GP_REGS + + // Record the type of exception that occurred. + mov x0, #\val + + // Jump to our general handler to deal with all the common parts and process the exception. + ldr x1, =ASM_PFX(CommonExceptionEntry) + br x1 + .ltorg + .endm + // // Current EL with SP0 : 0x0 - 0x180 // VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SP0_SYNC) ASM_PFX(SynchronousExceptionSP0): - b ASM_PFX(SynchronousExceptionEntry) + ExceptionEntry EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SP0_IRQ) ASM_PFX(IrqSP0): - b ASM_PFX(IrqEntry) + ExceptionEntry EXCEPT_AARCH64_IRQ VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SP0_FIQ) ASM_PFX(FiqSP0): - b ASM_PFX(FiqEntry) + ExceptionEntry EXCEPT_AARCH64_FIQ VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SP0_SERR) ASM_PFX(SErrorSP0): - b ASM_PFX(SErrorEntry) + ExceptionEntry EXCEPT_AARCH64_SERROR // // Current EL with SPx: 0x200 - 0x380 // VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPx_SYNC) ASM_PFX(SynchronousExceptionSPx): - b ASM_PFX(SynchronousExceptionEntry) + ExceptionEntry EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPx_IRQ) ASM_PFX(IrqSPx): - b ASM_PFX(IrqEntry) + ExceptionEntry EXCEPT_AARCH64_IRQ VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPx_FIQ) ASM_PFX(FiqSPx): - b ASM_PFX(FiqEntry) + ExceptionEntry EXCEPT_AARCH64_FIQ VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPx_SERR) ASM_PFX(SErrorSPx): - b ASM_PFX(SErrorEntry) + ExceptionEntry EXCEPT_AARCH64_SERROR // // Lower EL using AArch64 : 0x400 - 0x580 // VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_LOW_A64_SYNC) ASM_PFX(SynchronousExceptionA64): - b ASM_PFX(SynchronousExceptionEntry) + ExceptionEntry EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_LOW_A64_IRQ) ASM_PFX(IrqA64): - b ASM_PFX(IrqEntry) + ExceptionEntry EXCEPT_AARCH64_IRQ VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_LOW_A64_FIQ) ASM_PFX(FiqA64): - b ASM_PFX(FiqEntry) + ExceptionEntry EXCEPT_AARCH64_FIQ VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_LOW_A64_SERR) ASM_PFX(SErrorA64): - b ASM_PFX(SErrorEntry) + ExceptionEntry EXCEPT_AARCH64_SERROR // // Lower EL using AArch32 : 0x600 - 0x780 // VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_LOW_A32_SYNC) ASM_PFX(SynchronousExceptionA32): - b ASM_PFX(SynchronousExceptionEntry) + ExceptionEntry EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_LOW_A32_IRQ) ASM_PFX(IrqA32): - b ASM_PFX(IrqEntry) + ExceptionEntry EXCEPT_AARCH64_IRQ VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_LOW_A32_FIQ) ASM_PFX(FiqA32): - b ASM_PFX(FiqEntry) + ExceptionEntry EXCEPT_AARCH64_FIQ VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_LOW_A32_SERR) ASM_PFX(SErrorA32): - b ASM_PFX(SErrorEntry) + ExceptionEntry EXCEPT_AARCH64_SERROR VECTOR_END(ExceptionHandlersStart) -#undef REG_PAIR -#undef REG_ONE -#define REG_PAIR(REG1, REG2, OFFSET, CONTEXT_SIZE) stp REG1, REG2, [sp, #(OFFSET-CONTEXT_SIZE)] -#define REG_ONE(REG1, OFFSET, CONTEXT_SIZE) stur REG1, [sp, #(OFFSET-CONTEXT_SIZE)] - -ASM_PFX(SynchronousExceptionEntry): - // Move the stackpointer so we can reach our structure with the str instruction. - sub sp, sp, #(FP_CONTEXT_SIZE + SYS_CONTEXT_SIZE) - - // Save all the General regs before touching x0 and x1. - // This does not save r31(SP) as it is special. We do that later. - ALL_GP_REGS - - // Record the type of exception that occurred. - mov x0, #EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS - - // Jump to our general handler to deal with all the common parts and process the exception. - ldr x1, ASM_PFX(CommonExceptionEntry) - br x1 - -ASM_PFX(IrqEntry): - sub sp, sp, #(FP_CONTEXT_SIZE + SYS_CONTEXT_SIZE) - ALL_GP_REGS - mov x0, #EXCEPT_AARCH64_IRQ - ldr x1, ASM_PFX(CommonExceptionEntry) - br x1 - -ASM_PFX(FiqEntry): - sub sp, sp, #(FP_CONTEXT_SIZE + SYS_CONTEXT_SIZE) - ALL_GP_REGS - mov x0, #EXCEPT_AARCH64_FIQ - ldr x1, ASM_PFX(CommonExceptionEntry) - br x1 - -ASM_PFX(SErrorEntry): - sub sp, sp, #(FP_CONTEXT_SIZE + SYS_CONTEXT_SIZE) - ALL_GP_REGS - mov x0, #EXCEPT_AARCH64_SERROR - ldr x1, ASM_PFX(CommonExceptionEntry) - br x1 - - -// -// This gets patched by the C code that patches in the vector table -// -.align 3 -ASM_PFX(CommonExceptionEntry): - .8byte ASM_PFX(AsmCommonExceptionEntry) - ASM_PFX(ExceptionHandlersEnd): - -// -// This code runs from CpuDxe driver loaded address. It is patched into -// CommonExceptionEntry. -// -ASM_PFX(AsmCommonExceptionEntry): +ASM_PFX(CommonExceptionEntry): /* NOTE: We have to break up the save code because the immediate value to be used with the SP is too big to do it all in one step so we need to shuffle the SP