From patchwork Fri Mar 4 14:46:30 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Laszlo Ersek X-Patchwork-Id: 63598 Delivered-To: patch@linaro.org Received: by 10.112.199.169 with SMTP id jl9csp116544lbc; Fri, 4 Mar 2016 06:46:45 -0800 (PST) X-Received: by 10.66.65.109 with SMTP id w13mr12532560pas.142.1457102804433; Fri, 04 Mar 2016 06:46:44 -0800 (PST) Return-Path: Received: from ml01.01.org (ml01.01.org. [2001:19d0:306:5::1]) by mx.google.com with ESMTPS id g85si2489479pfj.135.2016.03.04.06.46.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 04 Mar 2016 06:46:44 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 41CB41A1EE1; Fri, 4 Mar 2016 06:46:54 -0800 (PST) X-Original-To: edk2-devel@ml01.01.org Delivered-To: edk2-devel@ml01.01.org Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 199911A1ECD for ; Fri, 4 Mar 2016 06:46:53 -0800 (PST) Received: from int-mx14.intmail.prod.int.phx2.redhat.com (int-mx14.intmail.prod.int.phx2.redhat.com [10.5.11.27]) by mx1.redhat.com (Postfix) with ESMTPS id 526A0DB00B; Fri, 4 Mar 2016 14:46:42 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-113-60.phx2.redhat.com [10.3.113.60]) by int-mx14.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id u24EkbP1018836; Fri, 4 Mar 2016 09:46:40 -0500 From: Laszlo Ersek To: edk2-devel@ml01.01.org Date: Fri, 4 Mar 2016 15:46:30 +0100 Message-Id: <1457102794-25499-2-git-send-email-lersek@redhat.com> In-Reply-To: <1457102794-25499-1-git-send-email-lersek@redhat.com> References: <1457102794-25499-1-git-send-email-lersek@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.68 on 10.5.11.27 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.39]); Fri, 04 Mar 2016 14:46:42 +0000 (UTC) Cc: Marcel Apfelbaum , Jordan Justen , Gabriel Somlo , =?UTF-8?q?Micha=C5=82=20Zegan?= Subject: [edk2] [PATCH 1/5] OvmfPkg: IndustryStandard/Q35MchIch9.h: add PCIEXBAR macros X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.17 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Section 5.1.16 ("PCIEXBAR -- PCI Express Register Range Base Address") in Intel document #316966-002 (already referenced near the top of this header file) describes the Q35 DRAM Controller register that configures the memory-mapped PCI config space (also known as MMCONFIG, and ECAM / Enhanced Configuration Access Method). In this patch we add the macros we'll need later. We'll only support the 256 MB memory-mapped config space -- enough for buses [0, 255]. Cc: Gabriel Somlo Cc: Jordan Justen Cc: Marcel Apfelbaum Cc: Michał Zegan Ref: https://github.com/tianocore/edk2/issues/32 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek --- OvmfPkg/Include/IndustryStandard/Q35MchIch9.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h b/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h index 18b34a3d4f4e..4dc2c39901c1 100644 --- a/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h +++ b/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h @@ -33,6 +33,14 @@ #define MCH_GGC 0x52 #define MCH_GGC_IVD BIT1 +#define MCH_PCIEXBAR_LOW 0x60 +#define MCH_PCIEXBAR_LOWMASK 0x0FFFFFFF +#define MCH_PCIEXBAR_BUS_FF 0 +#define MCH_PCIEXBAR_EN BIT0 + +#define MCH_PCIEXBAR_HIGH 0x64 +#define MCH_PCIEXBAR_HIGHMASK 0xFFFFFFF0 + #define MCH_SMRAM 0x9D #define MCH_SMRAM_D_LCK BIT4 #define MCH_SMRAM_G_SMRAME BIT3