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client-ip=2607:f8b0:4864:20::42a; helo=mail-pf1-x42a.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pf1-x42a.google.com (mail-pf1-x42a.google.com [IPv6:2607:f8b0:4864:20::42a]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id C35B92194D3B8 for ; Fri, 1 Feb 2019 05:35:16 -0800 (PST) Received: by mail-pf1-x42a.google.com with SMTP id i12so3225309pfo.7 for ; Fri, 01 Feb 2019 05:35:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=OG/4KcbZVe96k/u5gnHOCureem3n8CV2vDNi5pSETc0=; b=gZ2HGmMHiNbd9fzoxFeOZJsYlWN720VXTyJUhUkt7Lhz8veRG1Ow4DcdBtOgn6P+sj Atx4Vh3OvNzMvSyZ5X0LKLMrkfXNg/i2cFTSBrUlS1nolokdL1SB9zo5EmNsDXb8naHn /EWH4uye3DlGuTGmeHgZx6M77Wz8cA+JKHv8o= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; 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2 Modify for M7 self-Adapte support; 3 Add PCI_OSC_SUPPORT for ACPI/DSDT; 4 Change HCCS speed from 30G to 26G; 5 Rename StartupAp() function; 6 Fix access variable fail issue; 7 Optimize SAS driver for reducing boot time; 8 Add DriverHealthManagerDxe; 9 Remove useless code; Code can also be found in github: https://github.com/hisilicon/OpenPlatformPkg.git branch: 1902-platforms-v1 Jason Zhang (2): Hisilicon/D06: Fix access variable fail issue Hisilicon/D06: Add more PCIe port INT-x support Ming Huang (13): Hisilicon/D0x: Remove SerdesLib Hisilicon/D0x: Add DriverHealthManagerDxe Hisilicon/D06: Optimize SAS driver for reducing boot time Hisilicon/D0x: Rename StartupAp() function Hisilicon/D06: Change HCCS speed from 30G to 26G Hisilicon/D06: Add PCI_OSC_SUPPORT Hisilicon/D06: Modify for M7 self-Adapte support Hisilicon/D06: Add Setup Item "Support DPC" Hisilicon/D06: Use new flash layout Hisilicon/D06: Remove SECURE_BOOT_ENABLE definition Hisilicon/D0x: Remove SP805 watchdog pcd Hisilicon/D06: Use CalculateCrc16 in BaseLib Hisilicon/D0x: Modify version to 19.02 xingjiang tang (1): Hisilicon/D06: Add OemGetCpuFreq to encapsulate difference Platform/Hisilicon/D03/D03.dsc | 8 +- Platform/Hisilicon/D05/D05.dsc | 8 +- Platform/Hisilicon/D06/D06.dsc | 19 +- Platform/Hisilicon/D03/D03.fdf | 1 + Platform/Hisilicon/D05/D05.fdf | 1 + Platform/Hisilicon/D06/D06.fdf | 18 +- Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf | 1 - Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.inf | 1 - Platform/Hisilicon/D06/Include/Library/CpldD06.h | 4 + Silicon/Hisilicon/Include/Library/OemConfigData.h | 1 + Silicon/Hisilicon/Include/Library/OemMiscLib.h | 12 + Silicon/Hisilicon/Include/Library/PlatformSysCtrlLib.h | 2 +- Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr | 4 +- Platform/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.c | 2 +- Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c | 2 +- Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c | 2 +- Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c | 3 +- Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.c | 2 +- Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c | 24 ++ Platform/Hisilicon/D06/Library/OemNicLib/OemNicLib.c | 341 +++----------------- Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c | 6 +- Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl | 129 +++++++- Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr | 197 +---------- Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni | 3 +- 24 files changed, 238 insertions(+), 553 deletions(-) -- 2.9.5 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel