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[198.145.21.10]) by mx.google.com with ESMTPS id o81si1676780pfk.67.2018.02.28.11.24.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 28 Feb 2018 11:24:39 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=EvJWYBOv; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 28B042235228E; Wed, 28 Feb 2018 11:18:31 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::22a; helo=mail-wm0-x22a.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x22a.google.com (mail-wm0-x22a.google.com [IPv6:2a00:1450:400c:c09::22a]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id EE96721F6A6FC for ; Wed, 28 Feb 2018 11:18:28 -0800 (PST) Received: by mail-wm0-x22a.google.com with SMTP id t74so7199773wme.3 for ; Wed, 28 Feb 2018 11:24:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=RkK1Qos2DcltEuZAQnmdbO0EwVTjbJDIXOfVS5o61eI=; b=EvJWYBOvrcPeakBGKIEp2C5TyK70HNky9yAuEt1bZ17DLTPGPeuo3fWP0rmt/mUsRt ewR/3aCelal7oyo6aof7r5YX7hTCrBVn+2ojrso0nHxbVBB8FOjdOowOXV12wKmSIas/ fGsDaZPDZU+EgVju4KhnNK4SDBNz0Q7v4+b68= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=RkK1Qos2DcltEuZAQnmdbO0EwVTjbJDIXOfVS5o61eI=; b=aRqTPfeEH6fiVC6RhrByqNBCikydQ2pxH50m8WYb1rxkqDEl+v8nY9IQRKh6zU6F58 HLksJyjDdSfNl224PH7w293GbJIxmd5L/AfywUAf7NlCq3SqrAxSMBfHtLxNX/At59Yk HguM+6c6JrZhFBJjgxwtQH5SEbT1AFKkio2FTtEc0K2cYtidE2erE1wlqXAPHlEZfNeW s5LLbp9OUY2TRQ8jsUuGj6LWIckyQvtaBMfjX0IHypwynd+0nicaQI6KCfmFGugzRrwC T0+nBGwRaJeqPL48B410lE23BH/QPoK7wcn7xDPYbPZuX9q/m0jHkNHYabbrrkklhyWm g26w== X-Gm-Message-State: APf1xPC3J7EUu9P7S77b+/Uh+BcEx/JXQWozQ6PGX6u2Z1CIKF6zuYwA dwLnN7NW0rRWbXZ2k1ZEavtGgzHO+lA= X-Received: by 10.28.52.4 with SMTP id b4mr16675879wma.90.1519845874279; Wed, 28 Feb 2018 11:24:34 -0800 (PST) Received: from localhost.localdomain ([160.163.57.8]) by smtp.gmail.com with ESMTPSA id 47sm2152312wrb.48.2018.02.28.11.24.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 28 Feb 2018 11:24:32 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Wed, 28 Feb 2018 19:24:14 +0000 Message-Id: <20180228192421.17684-1-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 Subject: [edk2] [PATCH edk2-platforms v2 0/7] SynQuacer ACPI support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: masahisa.kojima@linaro.org, leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" This implements ACPI support for the SynQuacer platforms. Changes since v1: - improve commit log (#1, #2) - replace bare numbers with symbolic constants (#2) - add Leif's R-b (#4) - add patches #6 and #7 Note that supporting ACPI on this SoC is non-trivial, due to the quirky DesignWare RCs and the pre-ITS that sits between the PCIe RCs and the GICv3. However, the most important issue has been addressed by modifying the static SMMU mapping that sits between the CPUs and the PCIe config space, working around the ghosting issue that occurs on these RCs, due the complete lack of type 0 config TLP filtering by the [non-existent] root port. (This was tested using the 20180226-LB1.1-ACPI-ramfw.bin SCP firmware image, which is not [yet] installed by default on DeveloperBox hardware) That leaves the MSI issue, which is worked around by limiting MSI support to a single RC. In the presented configuration, this is RC #1, which connects to the x16 slot [and nothing else] on the DeveloperBox PCB. The onboard PCIe devices (XHCI + SATA) work without problem using wired interrupts only, and so RC #0 has MSI support disabled. This means cards that require MSI support should be inserted into the x16 slot, which is likely to be the preferred slot in such cases anwyay (e.g., when using NVME or high end networking plugin cards) Patch #1 fixes a minor issue in the slot-to-BDF mapping. Patch #2 modifies the static PCIe window configuration so it can be described using ACPI as well as DT. Patch #3 introduces the static ACPI tables that describe the fixed platform devices and peripherals to the OS. Patch #4 adds a menu option to the platform driver to make ACPI vs DT user selectable. Patch #5 adds support for describing the eMMC controller using a SSDT table which is only installed if eMMC support is enabled. Patch #6 adds a _STA method implementation to the PCIe RC devices so that they are only exposed to the OS when running on a platform that has one of the several ECAM workarounds enabled. Otherwise, we can still boot via ACPI using platform devices, but the PCIe RCs are unavailable. Patch #7 extends the _STA method for PCI0 to take the presence detect GPIO into account. This is necessary because on the SynQuacer evaluation board, any attempt to access the device registers will lock up the system if no card is inserted into the slot. Note that driver support for the eMMC and network controller only landed in v4.15, but when using a SATA driver and a plugin network card that does have driver support, these patches should allow the SynQuacer based platforms to boot stock Debian Stretch/Fedora/Centos etc installers. Ard Biesheuvel (7): Platform/Socionext/DeveloperBox: fix PCIe slot to B/D/F mapping Silicon/SynQuacer: tweak PCI I/O windows for ACPI/Linux support Silicon/SynQuacer: add ACPI drivers and tables Silicon/SynQuacer/PlatformDxe: add option to enable ACPI mode Silicon/SynQuacer/PlatformDxe: add ACPI description of eMMC Silicon/SynQuacer/AcpiTables: disable PCI RCs if ECAM ghosts are detected Silicon/SynQuacer/AcpiTables: take presence detect of PCI0 into account Platform/Socionext/DeveloperBox/DeveloperBox.dsc | 2 + Platform/Socionext/DeveloperBox/DeveloperBox.fdf | 14 + Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc | 2 + Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf | 14 + Silicon/Socionext/SynQuacer/Acpi.dsc.inc | 48 +++ Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl | 317 ++++++++++++++++++++ Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.h | 73 +++++ Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.inf | 65 ++++ Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl | 187 ++++++++++++ Silicon/Socionext/SynQuacer/AcpiTables/Fadt.aslc | 91 ++++++ Silicon/Socionext/SynQuacer/AcpiTables/Gtdt.aslc | 93 ++++++ Silicon/Socionext/SynQuacer/AcpiTables/Iort.aslc | 101 +++++++ Silicon/Socionext/SynQuacer/AcpiTables/Madt.aslc | 182 +++++++++++ Silicon/Socionext/SynQuacer/AcpiTables/Mcfg.aslc | 63 ++++ Silicon/Socionext/SynQuacer/AcpiTables/Spcr.aslc | 128 ++++++++ Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 2 +- Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.asl | 41 +++ Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c | 55 ++++ Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c | 32 +- Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h | 4 + Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf | 5 + Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.uni | 8 +- Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.vfr | 10 +- Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h | 22 +- Silicon/Socionext/SynQuacer/Include/Platform/VarStore.h | 8 +- Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c | 4 +- 26 files changed, 1546 insertions(+), 25 deletions(-) create mode 100644 Silicon/Socionext/SynQuacer/Acpi.dsc.inc create mode 100644 Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl create mode 100644 Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.h create mode 100644 Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.inf create mode 100644 Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl create mode 100644 Silicon/Socionext/SynQuacer/AcpiTables/Fadt.aslc create mode 100644 Silicon/Socionext/SynQuacer/AcpiTables/Gtdt.aslc create mode 100644 Silicon/Socionext/SynQuacer/AcpiTables/Iort.aslc create mode 100644 Silicon/Socionext/SynQuacer/AcpiTables/Madt.aslc create mode 100644 Silicon/Socionext/SynQuacer/AcpiTables/Mcfg.aslc create mode 100644 Silicon/Socionext/SynQuacer/AcpiTables/Spcr.aslc create mode 100644 Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.asl -- 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Leif Lindholm Reviewed-by: Graeme Gregory