From patchwork Tue Dec 12 10:37:59 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 121500 Delivered-To: patch@linaro.org Received: by 10.80.152.193 with SMTP id j59csp3890502edb; Tue, 12 Dec 2017 02:38:19 -0800 (PST) X-Google-Smtp-Source: ACJfBosJh/KP8wgdIGcZfn/IGvVig/K+shhepcChkb4g06XaAbCEkvQvCPZ+H7ha2wZUVpeYlDtd X-Received: by 10.84.198.67 with SMTP id o61mr1751392pld.261.1513075099679; Tue, 12 Dec 2017 02:38:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1513075099; cv=none; d=google.com; s=arc-20160816; b=eQ+g2BN4Okq1RapZhU32EHABBXzb9OAKSkiZRrEgB2D6TAoLF9blZwUdnwXAXVdh3l v1+fWqSgOrTO4bKpe9BdquxTcdz5EuVDv3Y0HxNCB3Hc5jMCFHSsRGTmQ/HIANGW++k8 IgYDZzatcVaUZ22k8ddplEiAByOtsfPrVbjLifvqhPLFIBTY1fdicmETktvZQKZDjwb1 +jmtqEDgN4XeE2OACoVNDAtqLkvqfPcuX1Kx/toxqiTtCa5gn9ZEc27Y1YT/1+g5vW6X i5fAYloKusKFQQwX2U0/iYK0LI2KT0cXH+kP3rlKV2g7q9j57+7HJvrWQqL/FWguv55v GcSw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:message-id:date:to:from:dkim-signature :delivered-to:arc-authentication-results; bh=Ia4FlwMWTaKluxmaTnuqaT4pgOxKjWhMwMaFWSEC+oY=; b=ys4N6qnsayKyVV5yAPzA9z4cq161ms3NC44vtHOAgI9t9vmgMSkF7sYi56knsRi4Ne UjDE+ohnpIqXPPhE1ToBCQjTtx3FSeR1EZ6fmoiE5lJkndp7pFl71X4Kj3Zrh7kNTIDB Xq4yLqv998dMyfB/zyWOavFV5sdupHnu7tprd5QHNLbCihuwZRUItDCTtAQ9EC/IXMfk oFxZpOEKKUKWsjhlkfu87U90fi3zba/LFkjNqDqTNT/NLdCFA0aKLI9Z/zMRMDHOygT4 pPjNHpLwQhrUud2pfViesnfYVh0f1D+f95yg52kHBt4G/1wPAAKD5f7DK1vnkHf46v2z WaMw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=FncrBO0P; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. 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client-ip=2a00:1450:400c:c0c::241; helo=mail-wr0-x241.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x241.google.com (mail-wr0-x241.google.com [IPv6:2a00:1450:400c:c0c::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id AEBB421A1099A for ; Tue, 12 Dec 2017 02:33:38 -0800 (PST) Received: by mail-wr0-x241.google.com with SMTP id k61so20570231wrc.4 for ; Tue, 12 Dec 2017 02:38:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=bqHwrkRACWODM/6MXPflNi0U3dYyAmkMsJo3n20cmA4=; b=FncrBO0PHj9OY3sFVY80KfSx9cmaf64cOML9LaECf7k3/ros6u8yAw473v09+yaLNC ZAgBRqFby4HA0wNRtqsK+X+i6cmEr4lGMTEJlaVBuDmmBrpzesQ91sGuU1wQLimatDEJ uxHLGFGeZNDx7nahpWQyYtffTHrQI03lf5vuM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=bqHwrkRACWODM/6MXPflNi0U3dYyAmkMsJo3n20cmA4=; b=oNtkcPzNXvC1KtRGhIz3w16BykeeyxMIa1O2DlEyAtuJzr53+hyyUlgc1/neBCXsXq dhFkmVOTw+JEYwYx4oQroA6GP031I6uB+29xWAd0aMTTo5OvIdXWRke74lrchgNgW9nF Hf+uszJRMxqxHx9B1BzdQHDA1yT/hTSmVJFhwgYkj24jhIFubCr6RQ9eg0+X+2Ggth89 xZwfBlcx1LFRwh+RK1dgYDTsSjXK5M5bUssVptkH4Z0yxisVznJAdswBWohtTURLbzq1 O8grwcoUyrJ+jizZtUuhEaSzUEdPbikVLmgN/HfgmNyaHFCUmxD7mCk5eNW1U0m2I/Ub oRrg== X-Gm-Message-State: AKGB3mIRueoL5Ixc0tA7s3Hv9KsEuRl5wsTm2oJFK3sVXScBcJGPuNnN 16gtTOpqAiXvTrMydKCIQnVZNapXTJs= X-Received: by 10.223.132.129 with SMTP id 1mr3287441wrg.136.1513075094900; Tue, 12 Dec 2017 02:38:14 -0800 (PST) Received: from localhost.localdomain ([160.171.158.223]) by smtp.gmail.com with ESMTPSA id b16sm21279762wrd.69.2017.12.12.02.38.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 Dec 2017 02:38:14 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Tue, 12 Dec 2017 10:37:59 +0000 Message-Id: <20171212103807.18836-1-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 Subject: [edk2] [PATCH edk2-platforms 0/8] SynQuacer updates X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: daniel.thompson@linaro.org, masami.hiramatsu@linaro.org, leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" A round of updates for Socionext SynQuacer: - enable CPU idle states in the DT, so that the OS can put cores to sleep using PSCI (#1) - add the build number to PCDs that end up in user visible strings (#2) - fix a PCIe detection issue in the DeveloperBox x16 slot, by keeping PERST# asserted for at least 100 ms before link training (#3) - ignore PCIe RC #0 if no card is inserted on EVB (#4 - #6) - add the secondary UART to the DT for the OS to use (this is UART #0 on the LS connector on DeveloperBox) (#7) - explicitly retrain the downstream links on the Asmedia 1182/1184 PCIe switch, to enable Gen2 speeds Ard Biesheuvel (7): Silicon/SynQuacer: enable CPU idle states in device tree Platform/Socionext/SynQuacer: expose build number as firmware version Silicon/SynQuacerPciHostBridgeLib: stall for 150 ms during PERST# Silicon/SynQuacerPciHostBridgeLib: enable RCs based on PCD setting Silicon/SynQuacer: disable PCI RC #0 DT node if disabled Silicon/SynQuacerEvalBoard: enable PCI #0 only when card is detected Silicon/SynQuacer/PlatformDxe: retrain PCIe switch links to Gen2 speed Masahisa KOJIMA (1): Silicon/Socionext/SynQuacer/DeviceTree: expose SCP serial port to the OS Platform/Socionext/DeveloperBox/DeveloperBox.dsc | 16 ++- Platform/Socionext/DeveloperBox/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf | 1 + Platform/Socionext/DeveloperBox/SystemFirmwareDescriptor/SystemFirmwareDescriptorTable.aslc | 6 +- Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc | 18 ++- Platform/Socionext/SynQuacerEvalBoard/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf | 1 + Platform/Socionext/SynQuacerEvalBoard/SystemFirmwareDescriptor/SystemFirmwareDescriptorTable.aslc | 6 +- Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 57 ++++---- Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Pcie.c | 140 ++++++++++++++++++++ Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c | 13 +- Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h | 37 ++++++ Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf | 3 + Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.c | 94 +++++++++++++ Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.inf | 42 ++++++ Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c | 19 ++- Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf | 4 + Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c | 58 +++++--- Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.c | 70 +++++++--- Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.inf | 2 + Silicon/Socionext/SynQuacer/SynQuacer.dec | 5 + 19 files changed, 504 insertions(+), 88 deletions(-) create mode 100644 Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Pcie.c create mode 100644 Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h create mode 100644 Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.c create mode 100644 Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.inf -- 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Leif Lindholm