| Message ID | 1519887444-75510-1-git-send-email-heyi.guo@linaro.org |
|---|---|
| Headers | show |
| Series | Add translation support to generic PciHostBridge | expand |
On 1 March 2018 at 06:57, Heyi Guo <heyi.guo@linaro.org> wrote: > Patch v5 inherits the code from RFC v4; we don't restart the version number for > RFC to PATCH change. > > v5: > - Patch 4/6: Modify the code according to the comments from Ray. > - Patch 1/6 and 2/6 are totally new. They add initialization for all fields of > PCI_ROOT_BRIDGE_APERTURE temporary variables in PciHostBridgeLib instances, so > that they will not suffer from extension of PCI_ROOT_BRIDGE_APERTURE > structure. > - Generate a separate patch (3/6) for PciHostBridgeLib.h change. Though it is a > prerequisite for patch 4/6, it does not change the code in PciHostBridge > driver and won't cause any build failure or functional issue. > > > v4: > - Modify the code according to the comments from Ray, Laszlo and Ard (Please see > the notes of Patch 1/3) > - Ignore translation of bus in CreateRootBridge. > > > v3: > - Keep definition of Translation consistent in EDKII code: Translation = device > address - host address. > - Patch 2/2 is split into 2 patches (2/3 and 3/3). > - Refine comments and commit messages to make the code easier to understand. > > > v2: > Changs are made according to the discussion on the mailing list, including: > > - PciRootBridgeIo->Configuration should return CPU view address, as well as > PciIo->GetBarAttributes, and Translation Offset should be equal to PCI view > address - CPU view address. > - Add translation offset to PCI_ROOT_BRIDGE_APERTURE structure definition. > - PciHostBridge driver internally used Base Address is still based on PCI view > address, and translation offset = CPU view - PCI view, which follows the > definition in ACPI, and not the same as that in UEFI spec. > Heyi, Thanks again for taking the time to implement this. I have applied the patches and they appear to work on my SynQuacer system, which has two PCIe RCs of which one uses translation for the I/O space I.e., PCI0 has 0x0..0xffff mapped to MMIO offset 0x67f00000 PCI1 has 0x0..0xffff mapped to MMIO offset 0x77f00000 The only problem I am hitting now is that the 'mm' shell command has a hard coded 16-bit limit for IO space, which we should probably fix as well. If I remove this limit, I can correctly access the I/O space of PCI1 like this: Shell> mm 77f00010 MEM 0x0000000077F00010 : 0x00 > MEM 0x0000000077F00011 : 0x03 > MEM 0x0000000077F00012 : 0x00 > MEM 0x0000000077F00013 : 0x00 > MEM 0x0000000077F00014 : 0x00 > MEM 0x0000000077F00015 : 0xF0 > MEM 0x0000000077F00016 : 0x35 > MEM 0x0000000077F00017 : 0xFD > q Shell> mm 10010 -io IO 0x0000000000010010 : 0x00 > IO 0x0000000000010011 : 0x03 > IO 0x0000000000010012 : 0x00 > IO 0x0000000000010013 : 0x00 > IO 0x0000000000010014 : 0x00 > IO 0x0000000000010015 : 0xF0 > IO 0x0000000000010016 : 0x35 > IO 0x0000000000010017 : 0xFD > q Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> > Cc: Ruiyu Ni <ruiyu.ni@intel.com> > Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> > Cc: Star Zeng <star.zeng@intel.com> > Cc: Eric Dong <eric.dong@intel.com> > Cc: Laszlo Ersek <lersek@redhat.com> > Cc: Michael D Kinney <michael.d.kinney@intel.com> > Cc: Maurice Ma <maurice.ma@intel.com> > Cc: Prince Agyeman <prince.agyeman@intel.com> > Cc: Benjamin You <benjamin.you@intel.com> > Cc: Jordan Justen <jordan.l.justen@intel.com> > Cc: Anthony Perard <anthony.perard@citrix.com> > Cc: Julien Grall <julien.grall@linaro.org> > > Heyi Guo (6): > CorebootPayloadPkg/PciHostBridgeLib: Init PCI aperture to 0 > OvmfPkg/PciHostBridgeLib: Init PCI aperture to 0 > MdeModulePkg/PciHostBridgeLib.h: add address Translation > MdeModulePkg/PciHostBridgeDxe: Add support for address translation > MdeModulePkg/PciBus: convert host address to device address > MdeModulePkg/PciBus: return CPU address for GetBarAttributes > > MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.h | 21 ++++ > MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostResource.h | 3 + > MdeModulePkg/Include/Library/PciHostBridgeLib.h | 19 +++ > CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c | 5 + > MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c | 12 +- > MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c | 129 +++++++++++++++++--- > MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c | 118 ++++++++++++++++-- > OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c | 4 + > OvmfPkg/Library/PciHostBridgeLib/XenSupport.c | 5 + > 9 files changed, 288 insertions(+), 28 deletions(-) > > -- > 2.7.4 > _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
On 3/1/2018 2:57 PM, Heyi Guo wrote: > Patch v5 inherits the code from RFC v4; we don't restart the version number for > RFC to PATCH change. > > v5: > - Patch 4/6: Modify the code according to the comments from Ray. > - Patch 1/6 and 2/6 are totally new. They add initialization for all fields of > PCI_ROOT_BRIDGE_APERTURE temporary variables in PciHostBridgeLib instances, so > that they will not suffer from extension of PCI_ROOT_BRIDGE_APERTURE > structure. > - Generate a separate patch (3/6) for PciHostBridgeLib.h change. Though it is a > prerequisite for patch 4/6, it does not change the code in PciHostBridge > driver and won't cause any build failure or functional issue. > > > v4: > - Modify the code according to the comments from Ray, Laszlo and Ard (Please see > the notes of Patch 1/3) > - Ignore translation of bus in CreateRootBridge. > > > v3: > - Keep definition of Translation consistent in EDKII code: Translation = device > address - host address. > - Patch 2/2 is split into 2 patches (2/3 and 3/3). > - Refine comments and commit messages to make the code easier to understand. > > > v2: > Changs are made according to the discussion on the mailing list, including: > > - PciRootBridgeIo->Configuration should return CPU view address, as well as > PciIo->GetBarAttributes, and Translation Offset should be equal to PCI view > address - CPU view address. > - Add translation offset to PCI_ROOT_BRIDGE_APERTURE structure definition. > - PciHostBridge driver internally used Base Address is still based on PCI view > address, and translation offset = CPU view - PCI view, which follows the > definition in ACPI, and not the same as that in UEFI spec. > > Cc: Ruiyu Ni <ruiyu.ni@intel.com> > Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> > Cc: Star Zeng <star.zeng@intel.com> > Cc: Eric Dong <eric.dong@intel.com> > Cc: Laszlo Ersek <lersek@redhat.com> > Cc: Michael D Kinney <michael.d.kinney@intel.com> > Cc: Maurice Ma <maurice.ma@intel.com> > Cc: Prince Agyeman <prince.agyeman@intel.com> > Cc: Benjamin You <benjamin.you@intel.com> > Cc: Jordan Justen <jordan.l.justen@intel.com> > Cc: Anthony Perard <anthony.perard@citrix.com> > Cc: Julien Grall <julien.grall@linaro.org> > > Heyi Guo (6): > CorebootPayloadPkg/PciHostBridgeLib: Init PCI aperture to 0 > OvmfPkg/PciHostBridgeLib: Init PCI aperture to 0 > MdeModulePkg/PciHostBridgeLib.h: add address Translation > MdeModulePkg/PciHostBridgeDxe: Add support for address translation > MdeModulePkg/PciBus: convert host address to device address > MdeModulePkg/PciBus: return CPU address for GetBarAttributes > > MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.h | 21 ++++ > MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostResource.h | 3 + > MdeModulePkg/Include/Library/PciHostBridgeLib.h | 19 +++ > CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c | 5 + > MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c | 12 +- > MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c | 129 +++++++++++++++++--- > MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c | 118 ++++++++++++++++-- > OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c | 4 + > OvmfPkg/Library/PciHostBridgeLib/XenSupport.c | 5 + > 9 files changed, 288 insertions(+), 28 deletions(-) > Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> -- Thanks, Ray _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel