From patchwork Tue May 12 06:48:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Simek X-Patchwork-Id: 245621 List-Id: U-Boot discussion From: michal.simek at xilinx.com (Michal Simek) Date: Tue, 12 May 2020 08:48:29 +0200 Subject: [PATCH 4/5] fpga: zynqpl: Flush dcache only for non-bitstream data In-Reply-To: References: Message-ID: From: T Karthik Reddy In case of aes decryption destination address range must be flushed before transferring decrypted data to destination. Signed-off-by: T Karthik Reddy Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- drivers/fpga/zynqpl.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c index a323733ef363..6fc5cf57238e 100644 --- a/drivers/fpga/zynqpl.c +++ b/drivers/fpga/zynqpl.c @@ -545,8 +545,9 @@ int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen, * Flush destination address range only if image is not * bitstream. */ - flush_dcache_range((u32)dstaddr, (u32)dstaddr + - roundup(dstlen << 2, ARCH_DMA_MINALIGN)); + if (bstype == BIT_NONE && dstaddr != 0xFFFFFFFF) + flush_dcache_range((u32)dstaddr, (u32)dstaddr + + roundup(dstlen << 2, ARCH_DMA_MINALIGN)); if (zynq_dma_transfer(srcaddr | 1, srclen, dstaddr | 1, dstlen)) return FPGA_FAIL;