From patchwork Tue Jan 21 03:46:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Anderson X-Patchwork-Id: 239831 List-Id: U-Boot discussion From: seanga2 at gmail.com (Sean Anderson) Date: Mon, 20 Jan 2020 22:46:20 -0500 Subject: [PATCH v2 08/11] riscv: Add device tree for K210 In-Reply-To: <3411d84b-5a56-ae4e-1deb-085ef1a4971d@gmail.com> References: <3411d84b-5a56-ae4e-1deb-085ef1a4971d@gmail.com> Message-ID: <73c4ca8d-e702-15fd-6804-ecace54c7be1@gmail.com> There is a mirror of ram located at 0x4000000 which is un-cached. This is probably useful for DMA, but I am unsure of how to describe it in this device tree. The cache-line size is undocumented. Emphirical tests suggest that it is 32 bytes, but I've used 64-bytes to be on the safe side. Where possible, I have tried to find compatible drivers based on the layout of registers. However, I have not tested most of this functionality, and anything aside from clint0, uarths0, and sysctl should be considered descriptive at best. I would appreciate if anyone could help identify possibly compatible devices, especially for the timers, watchdogs, and rtc. The documentation for pinconf devices indicates that #pinctrl-cells is a required property, but I am unsure what to put for it. Should that be filled in by a board-specific device tree? The sysctl device has multiple different unrelated registers. For the moment, I have split off sub-devices for each functionality. In addition to clock and reset control, it also contains DMA handshake registers, and power registers. I have not described those at the moment, and I would appreciate suggestions on how to best describe them. I'm not sure what the value of spi-max-frequency should be for external sd-card slots. Suggestions are appreciated. Signed-off-by: Sean Anderson --- arch/riscv/dts/Makefile | 1 + arch/riscv/dts/k210-maix-bit.dts | 42 +++ arch/riscv/dts/k210.dtsi | 453 ++++++++++++++++++++++++ board/sipeed/maix/Kconfig | 3 + configs/sipeed_maix_bitm_defconfig | 1 + include/dt-bindings/clock/k210-sysctl.h | 54 +++ include/dt-bindings/reset/k210-sysctl.h | 38 ++ 7 files changed, 592 insertions(+) create mode 100644 arch/riscv/dts/k210-maix-bit.dts create mode 100644 arch/riscv/dts/k210.dtsi create mode 100644 include/dt-bindings/clock/k210-sysctl.h create mode 100644 include/dt-bindings/reset/k210-sysctl.h diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index 4f30e6936f..3a6f96c67d 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -2,6 +2,7 @@ dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb dtb-$(CONFIG_TARGET_SIFIVE_FU540) += hifive-unleashed-a00.dtb +dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb targets += $(dtb-y) diff --git a/arch/riscv/dts/k210-maix-bit.dts b/arch/riscv/dts/k210-maix-bit.dts new file mode 100644 index 0000000000..a25aa34ff8 --- /dev/null +++ b/arch/riscv/dts/k210-maix-bit.dts @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Sean Anderson + */ + +/dts-v1/; + +#include "k210.dtsi" + +/ { + model = "Sipeed Maix Bit"; + compatible = "sipeed,maix-bit", "kendryte,k210"; + + chosen { + bootargs = "console=ttyS0,115200n8 debug loglevel=7"; + stdout-path = "serial0"; + }; +}; + +&uarths0 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + slot at 0 { + compatible = "mmc-spi-slot"; + reg = <0>; + broken-cd; + disable-wp; + }; +}; + +&spi3 { + status = "okay"; + spi-flash at 0 { + compatible = "gd25lq64c", "gd25q64", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <120000000>; + m25p,fast-read; + }; +}; diff --git a/arch/riscv/dts/k210.dtsi b/arch/riscv/dts/k210.dtsi new file mode 100644 index 0000000000..1408d9b4a9 --- /dev/null +++ b/arch/riscv/dts/k210.dtsi @@ -0,0 +1,453 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Sean Anderson + */ + +#include +#include + +/ { + /* + * Although the K210 is a 64-bit CPU, the address bus is only 32-bits + * wide, and the upper half of all addresses is ignored. + */ + #address-cells = <1>; + #size-cells = <1>; + compatible = "kendryte,k210"; + + aliases { + serial0 = &uarths0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; + spi3 = &spi3; + }; + + clocks { + in0: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <7800000>; + cpu0: cpu at 0 { + device_type = "cpu"; + reg = <0>; + compatible = "riscv"; + riscv,isa = "rv64acdfim"; + mmu-type = "riscv,sv32"; + i-cache-size = <0x8000>; + i-cache-block-size = <64>; /* bogus */ + d-cache-size = <0x8000>; + d-cache-block-size = <64>; /* bogus */ + clocks = <&sysclk K210_CLK_CPU>; + clock-frequency = <390000000>; + cpu0_intc: interrupt-controller { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + cpu1: cpu at 1 { + device_type = "cpu"; + reg = <1>; + compatible = "riscv"; + riscv,isa = "rv64acdfim"; + mmu-type = "riscv,sv32"; + i-cache-size = <0x8000>; + i-cache-block-size = <64>; /* bogus */ + d-cache-size = <0x8000>; + d-cache-block-size = <64>; /* bogus */ + clocks = <&sysclk K210_CLK_CPU>; + clock-frequency = <390000000>; + cpu1_intc: interrupt-controller { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + }; + + sram0: memory at 80000000 { + device_type = "memory"; + reg = <0x80000000 0x400000>; + clocks = <&sysclk K210_CLK_SRAM0>; + }; + + sram1: memory at 80400000 { + device_type = "memory"; + reg = <0x80400000 0x400000>; + clocks = <&sysclk K210_CLK_SRAM1>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + ai_reserved: ai at 80600000 { + reg = <0x80600000 0x200000>; + reusable; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "kendryte,k210-soc", "simple-bus"; + ranges; + interrupt-parent = <&plic0>; + + clint0: interrupt-controller at 2000000 { + compatible = "riscv,clint0"; + reg = <0x2000000 0xC000>; + interrupts-extended = <&cpu0_intc 3>, <&cpu1_intc 3>; + clocks = <&sysclk K210_CLK_CPU>; + }; + + plic0: interrupt-controller at c000000 { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "riscv,plic1"; + reg = <0xC000000 0x03FFF008>; + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>, + <&cpu1_intc 11>, <&cpu1_intc 9>; + riscv,ndev = <65>; + }; + + uarths0: serial at 38000000 { + compatible = "sifive,uart0"; + reg = <0x38000000 0x20>; + interrupts = <33>; + clocks = <&sysclk K210_CLK_CPU>; + status = "disabled"; + }; + + gpio0: gpio-controller at 38001000 { + #gpio-cells = <2>; + compatible = "none"; + reg = <0x38001000 0x44>; + gpio-controller; + interrupts = <34 35 36 37 38 39 40 41 + 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 + 58 59 60 61 62 63 64 65>; + clocks = <&sysclk K210_CLK_CPU>; + status = "disabled"; + }; + + kpu0: kpu at 40600000 { + compatible = "none"; + reg = <0x40800000 0x48>; + interrupts = <25>; + clocks = <&sysclk K210_CLK_AI>; + memory-region = <&ai_reserved>; + status = "disabled"; + }; + + fft0: fft at 42000000 { + compatible = "none"; + reg = <0x42000000 0x400000>; + interrupts = <26>; + clocks = <&sysclk K210_CLK_FFT>; + resets = <&sysrst K210_RST_FFT>; + status = "disabled"; + }; + + dmac0: dma-controller at 50000000 { + compatible = "snps,axi-dma-1.01a"; + reg = <0x50000000 0xD00>; + interrupts = <27 28 29 30 31 32>; + clocks = <&sysclk K210_CLK_DMA>, <&sysclk K210_CLK_DMA>; + clock-names = "core-clk", "cfgr-clk"; + resets = <&sysrst K210_RST_DMA>; + dma-channels = <6>; + snps,dma-masters = <2>; + snps,data-width = <5>; + snps,block-size = <0x400000 0x400000 0x400000 + 0x400000 0x400000 0x400000>; + snps,axi-max-burst-len = <256>; + status = "disabled"; + }; + + gpio1: gpio-controller at 50200000 { + #gpio-cells = <2>; + compatible = "none"; + reg = <0x50200000 0x6C>; + gpio-controller; + interrupts = <23>; + clocks = <&sysclk K210_CLK_GPIO>; + resets = <&sysrst K210_RST_GPIO>; + status = "disabled"; + }; + + uart1: serial at 50210000 { + compatible = "ns16550"; + reg = <50210000 0xc4>; + interrupts = <11>; + clocks = <&sysclk K210_CLK_UART1>; + resets = <&sysrst K210_RST_UART1>; + fifo-size = <8>; + no-loopback-test; + status = "disabled"; + }; + + uart2: serial at 50220000 { + compatible = "ns16550"; + reg = <50220000 0xc4>; + interrupts = <12>; + clocks = <&sysclk K210_CLK_UART2>; + resets = <&sysrst K210_RST_UART2>; + fifo-size = <8>; + no-loopback-test; + status = "disabled"; + }; + + uart3: serial at 50230000 { + compatible = "ns16550"; + reg = <50230000 0xc4>; + interrupts = <13>; + clocks = <&sysclk K210_CLK_UART3>; + resets = <&sysrst K210_RST_UART3>; + fifo-size = <8>; + no-loopback-test; + status = "disabled"; + }; + + spi2: spi at 50240000 { + compatible = "snps,dw-apb-ssi"; + spi-slave; + reg = <0x50240000 0x120>; + interrupts = <2>; + clocks = <&sysclk K210_CLK_SPI2>; + resets = <&sysrst K210_RST_SPI2>; + status = "disabled"; + }; + + i2s0: i2s at 50250000 { + compatible = "snps.designware-i2s"; + reg = <0x50250000 0x200>; + interrupts = <5>; + clocks = <&sysclk K210_CLK_I2S0>; + resets = <&sysrst K210_RST_I2S0>; + status = "disabled"; + }; + + apu0: sound at 520250200 { + compatible = "none"; + reg = <0x50250200 0x138>; + status = "disabled"; + }; + + i2s1: i2s at 50260000 { + compatible = "snps.designware-i2s"; + reg = <0x50260000 0x200>; + interrupts = <6>; + clocks = <&sysclk K210_CLK_I2S1>; + resets = <&sysrst K210_RST_I2S1>; + status = "disabled"; + }; + + i2s2: i2s at 50270000 { + compatible = "snps.designware-i2s"; + reg = <0x50270000 0x200>; + interrupts = <7>; + clocks = <&sysclk K210_CLK_I2S2>; + resets = <&sysrst K210_RST_I2S2>; + status = "disabled"; + }; + + i2c0: i2c at 50280000 { + compatible = "snps,designware-i2c"; + reg = <0x50280000 0x100>; + interrupts = <8>; + clocks = <&sysclk K210_CLK_I2C0>; + resets = <&sysrst K210_RST_I2C0>; + status = "disabled"; + }; + + i2c1: i2c at 50290000 { + compatible = "snps,designware-i2c"; + reg = <0x50290000 0x100>; + interrupts = <9>; + clocks = <&sysclk K210_CLK_I2C1>; + resets = <&sysrst K210_RST_I2C1>; + status = "disabled"; + }; + + + i2c2: i2c at 502A0000 { + compatible = "snps,designware-i2c"; + reg = <0x502A0000 0x100>; + interrupts = <10>; + clocks = <&sysclk K210_CLK_I2C2>; + resets = <&sysrst K210_RST_I2C2>; + status = "disabled"; + }; + + fpioa: pinmux at 502B0000 { + compatible = "pinconf-single"; + reg = <0x502B0000 0x100>; + //#pinctrl-cells = ; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x7fffff>; + clocks = <&sysclk K210_CLK_FPIOA>; + resets = <&sysrst K210_RST_FPIOA>; + status = "disabled"; + }; + + sha256: sha256 at 502C0000 { + compatible = "none"; + reg = <0x502C0000 0x38>; + clocks = <&sysclk K210_CLK_SHA>; + resets = <&sysrst K210_RST_SHA>; + status = "disabled"; + }; + + timer0: timer at 502D0000 { + compatible = "none"; + reg = <0x502D0000 0xC0>; + interrupts = <14 15>; + clocks = <&sysclk K210_CLK_TIMER0>; + resets = <&sysrst K210_RST_TIMER0>; + status = "disabled"; + }; + + timer1: timer at 502E0000 { + compatible = "none"; + reg = <0x502E0000 0xC0>; + interrupts = <16 17>; + clocks = <&sysclk K210_CLK_TIMER1>; + resets = <&sysrst K210_RST_TIMER1>; + status = "disabled"; + }; + + timer2: timer at 502F0000 { + compatible = "none"; + reg = <0x502F0000 0xC0>; + interrupts = <18 19>; + clocks = <&sysclk K210_CLK_TIMER2>; + resets = <&sysrst K210_RST_TIMER2>; + status = "disabled"; + }; + + wdt0: watchdog at 50400000 { + compatible = "none"; + reg = <0x50400000 0x100>; + interrupts = <21>; + clocks = <&sysclk K210_CLK_WDT0>; + resets = <&sysrst K210_RST_WDT0>; + status = "disabled"; + }; + + wdt1: watchdog at 50410000 { + compatible = "none"; + reg = <0x50410000 0x100>; + interrupts = <22>; + clocks = <&sysclk K210_CLK_WDT1>; + resets = <&sysrst K210_RST_WDT1>; + status = "disabled"; + }; + + dvp0: camera at 50430000 { + compatible = "none"; + reg = <0x50430000 0x2c>; + interrupts = <24>; + clocks = <&sysclk K210_CLK_DVP>; + resets = <&sysrst K210_RST_DVP>; + status = "disabled"; + }; + + sysctl: sysctl at 50440000 { + compatible = "kendryte,k210-sysctl", "syscon"; + reg = <0x50440000 0x80>; + + sysclk: clock-controller { + compatible = "kendryte,k210-clk"; + clocks = <&in0>; + #clock-cells = <1>; + }; + + sysrst: reset-controller { + compatible = "kendryte,k210-rst"; + #reset-cells = <1>; + }; + }; + + aes0: aes at 50450000 { + compatible = "none"; + reg = <0x50450000 0x94>; + clocks = <&sysclk K210_CLK_AES>; + resets = <&sysrst K210_RST_AES>; + status = "disabled"; + }; + + rtc: rts at 50460000 { + compatible = "none"; + reg = <0x50460000 0x2C>; + clocks = <&in0>; + resets = <&sysrst K210_RST_RTC>; + interrupts = <20>; + status = "disabled"; + }; + + spi0: spi at 52000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-ssi"; + reg = <0x52000000 0x120>; + interrupts = <1>; + clocks = <&sysclk K210_CLK_SPI0>; + clock-names = "ssi_clk"; + resets = <&sysrst K210_RST_SPI0>; + num-cs = <4>; + reg-io-width = <4>; + status = "disabled"; + }; + + spi1: spi at 53000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-ssi"; + reg = <0x53000000 0x120>; + interrupts = <2>; + clocks = <&sysclk K210_CLK_SPI1>; + clock-names = "ssi_clk"; + resets = <&sysrst K210_RST_SPI1>; + num-cs = <4>; + reg-io-width = <4>; + status = "disabled"; + }; + + spi3: spi at 54000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-ssi"; + reg = <0x54000000 0x120>; + interrupts = <4>; + clocks = <&sysclk K210_CLK_SPI3>; + clock-names = "ssi_clk"; + assigned-clocks = <&sysclk K210_CLK_SPI3>; + assigned-clock-parents = <&sysclk K210_CLK_PLL0>; + resets = <&sysrst K210_RST_SPI3>; + num-cs = <4>; + reg-io-width = <4>; + status = "disabled"; + }; + + rom0: nvmem at 88000000 { + reg = <0x88000000 0x4000>; + read-only; + clocks = <&sysclk K210_CLK_ROM>; + resets = <&sysrst K210_RST_ROM>; + }; + }; +}; diff --git a/board/sipeed/maix/Kconfig b/board/sipeed/maix/Kconfig index 9259eb34aa..efeaddf317 100644 --- a/board/sipeed/maix/Kconfig +++ b/board/sipeed/maix/Kconfig @@ -18,6 +18,9 @@ config SYS_CONFIG_NAME config SYS_TEXT_BASE default 0x80000000 +config DEFAULT_DEVICE_TREE + default "k210-maix-bit" + config NR_CPUS default 2 diff --git a/configs/sipeed_maix_bitm_defconfig b/configs/sipeed_maix_bitm_defconfig index f062cc8c58..ecd69c0873 100644 --- a/configs/sipeed_maix_bitm_defconfig +++ b/configs/sipeed_maix_bitm_defconfig @@ -15,6 +15,7 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_BOOTSTAGE_STASH_ADDR=0 CONFIG_64BIT=y CONFIG_TARGET_SIPEED_MAIX=y +CONFIG_DEFAULT_DEVICE_TREE="k210-maix-bit" CONFIG_NR_CPUS=2 CONFIG_GENERIC_RISCV=y CONFIG_ARCH_DEFAULT_RV64I=y diff --git a/include/dt-bindings/clock/k210-sysctl.h b/include/dt-bindings/clock/k210-sysctl.h new file mode 100644 index 0000000000..308974baf8 --- /dev/null +++ b/include/dt-bindings/clock/k210-sysctl.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 Sean Anderson + */ + +#ifndef CLOCK_K210_SYSCTL_H +#define CLOCK_K210_SYSCTL_H + +/* Clocks as defined by kendryte-standalone-sdk/lib/drivers/include/sysctl.h */ +#define K210_CLK_PLL0 0 +#define K210_CLK_PLL1 1 +#define K210_CLK_PLL2 2 +#define K210_CLK_CPU 3 +#define K210_CLK_SRAM0 4 +#define K210_CLK_SRAM1 5 +#define K210_CLK_APB0 6 +#define K210_CLK_APB1 7 +#define K210_CLK_APB2 8 +#define K210_CLK_ROM 9 +#define K210_CLK_DMA 10 +#define K210_CLK_AI 11 +#define K210_CLK_DVP 12 +#define K210_CLK_FFT 13 +#define K210_CLK_GPIO 14 +#define K210_CLK_SPI0 15 +#define K210_CLK_SPI1 16 +#define K210_CLK_SPI2 17 +#define K210_CLK_SPI3 18 +#define K210_CLK_I2S0 19 +#define K210_CLK_I2S1 20 +#define K210_CLK_I2S2 21 +#define K210_CLK_I2C0 22 +#define K210_CLK_I2C1 23 +#define K210_CLK_I2C2 24 +#define K210_CLK_UART1 25 +#define K210_CLK_UART2 26 +#define K210_CLK_UART3 27 +#define K210_CLK_AES 28 +#define K210_CLK_FPIOA 29 +#define K210_CLK_TIMER0 30 +#define K210_CLK_TIMER1 31 +#define K210_CLK_TIMER2 32 +#define K210_CLK_WDT0 33 +#define K210_CLK_WDT1 34 +#define K210_CLK_SHA 35 +#define K210_CLK_OTP 36 +#define K210_CLK_RTC 37 +#define K210_CLK_ACLK 40 +#define K210_CLK_MAX 40 + +#define K210_CLK_HCLK 41 /* Unused */ +#define K210_CLK_IN0 42 /* Defined elsewhere in the device tree */ + +#endif /* CLOCK_K210_SYSCTL_H */ diff --git a/include/dt-bindings/reset/k210-sysctl.h b/include/dt-bindings/reset/k210-sysctl.h new file mode 100644 index 0000000000..670e74daaf --- /dev/null +++ b/include/dt-bindings/reset/k210-sysctl.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 Sean Anderson + */ + +#ifndef RESET_K210_SYSCTL_H +#define RESET_K210_SYSCTL_H + +#define K210_RST_ROM 0 +#define K210_RST_DMA 1 +#define K210_RST_AI 2 +#define K210_RST_DVP 3 +#define K210_RST_FFT 4 +#define K210_RST_GPIO 5 +#define K210_RST_SPI0 6 +#define K210_RST_SPI1 7 +#define K210_RST_SPI2 8 +#define K210_RST_SPI3 9 +#define K210_RST_I2S0 10 +#define K210_RST_I2S1 11 +#define K210_RST_I2S2 12 +#define K210_RST_I2C0 13 +#define K210_RST_I2C1 14 +#define K210_RST_I2C2 15 +#define K210_RST_UART1 16 +#define K210_RST_UART2 17 +#define K210_RST_UART3 18 +#define K210_RST_AES 19 +#define K210_RST_FPIOA 20 +#define K210_RST_TIMER0 21 +#define K210_RST_TIMER1 22 +#define K210_RST_TIMER2 23 +#define K210_RST_WDT0 24 +#define K210_RST_WDT1 25 +#define K210_RST_SHA 26 +#define K210_RST_RTC 29 + +#endif /* RESET_K210_SYSCTL_H */