From patchwork Wed Dec 26 06:13:42 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Minkyu Kang X-Patchwork-Id: 13696 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 37A5923E1F for ; Wed, 26 Dec 2012 06:13:45 +0000 (UTC) Received: from mail-vb0-f52.google.com (mail-vb0-f52.google.com [209.85.212.52]) by fiordland.canonical.com (Postfix) with ESMTP id CE1C1A18FB2 for ; Wed, 26 Dec 2012 06:13:44 +0000 (UTC) Received: by mail-vb0-f52.google.com with SMTP id ez10so8573938vbb.11 for ; Tue, 25 Dec 2012 22:13:44 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:x-forwarded-to:x-forwarded-for:delivered-to:x-received :received-spf:x-auditid:message-id:date:from:organization:user-agent :mime-version:to:cc:subject:references:in-reply-to:content-type :content-transfer-encoding:dlp-filter:x-mtr:x-brightmail-tracker :x-brightmail-tracker:x-cfilter-loop:x-gm-message-state; bh=V9nMTd3sPpTE5L5CpeUu4klq7IOm8O+HMi15euUOG9k=; b=R0Wl/3UaFIanQxvNMjTc6cY4LtihEGfZe4X6HieFY7//JmpxFV3obKRCzH3zAga4mR WEtrmZk2OeOooZmFhGn3ngdm3+d3/PEZ61c1qcRD7JyxejfNU5BZobNOzjqcdq8QFO8u Odn8ifjLIyUPy/N+MtE+V7AQJyvNlxVs232GsSonCDSgdmJPNf/WnCdLi3zfBg/I++Kd MToguyP3unSKbSfBdY0ddmVKULhcIQsAfc1I75v4fVCLy2+4uq6oRX9G03WFBaWDCzKx 81uRqndEpjV+Qa0fsY1jpf0QBWqZfzfZ52YEerczb3LStmY2YfUmN6oMM7DjunyOEYQw JRjQ== X-Received: by 10.52.18.147 with SMTP id w19mr35112846vdd.94.1356502424284; Tue, 25 Dec 2012 22:13:44 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.58.49.133 with SMTP id u5csp250611ven; Tue, 25 Dec 2012 22:13:43 -0800 (PST) X-Received: by 10.66.85.70 with SMTP id f6mr69234734paz.76.1356502423202; Tue, 25 Dec 2012 22:13:43 -0800 (PST) Received: from mailout1.samsung.com (mailout1.samsung.com. [203.254.224.24]) by mx.google.com with ESMTP id tp3si25075979pbc.115.2012.12.25.22.13.42; Tue, 25 Dec 2012 22:13:43 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of mk7.kang@samsung.com designates 203.254.224.24 as permitted sender) client-ip=203.254.224.24; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of mk7.kang@samsung.com designates 203.254.224.24 as permitted sender) smtp.mail=mk7.kang@samsung.com Received: from epcpsbgm2.samsung.com (epcpsbgm2 [203.254.230.27]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MFM00AI5JYN49G0@mailout1.samsung.com>; Wed, 26 Dec 2012 15:13:42 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [203.254.230.44]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 55.49.12699.6959AD05; Wed, 26 Dec 2012 15:13:42 +0900 (KST) X-AuditID: cbfee61b-b7f616d00000319b-1a-50da95967938 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 15.49.12699.6959AD05; Wed, 26 Dec 2012 15:13:42 +0900 (KST) Received: from [10.90.45.134] by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MFM00DWUJYTDU00@mmp1.samsung.com>; Wed, 26 Dec 2012 15:13:42 +0900 (KST) Message-id: <50DA9596.4060403@samsung.com> Date: Wed, 26 Dec 2012 15:13:42 +0900 From: Minkyu Kang Organization: SAMSUNG ELECTRONICS User-Agent: Mozilla/5.0 (X11; Linux i686; rv:17.0) Gecko/17.0 Thunderbird/17.0 MIME-version: 1.0 To: Chander Kashyap , u-boot@lists.denx.de Cc: linaro-dev@lists.linaro.org, patches@linaro.org Subject: [PATCH v3 3/3] EXYNOS: EXYNOS4X12: Add gpio structure for EXYNOS4X12 References: <1354875686-31703-1-git-send-email-chander.kashyap@linaro.org> <1354875686-31703-4-git-send-email-chander.kashyap@linaro.org> In-reply-to: <1354875686-31703-4-git-send-email-chander.kashyap@linaro.org> Content-type: text/plain; charset=ISO-8859-1 Content-transfer-encoding: 7bit DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrKIsWRmVeSWpSXmKPExsVy+t8zHd1pU28FGOw9KWHxcP1NFosph7+w ODB53Lm2hy2AMYrLJiU1J7MstUjfLoEr48DhbWwFvXIV/f/+sDcwTpDsYuTkkBAwkdh+sp8d whaTuHBvPVsXIxeHkMAyRom307+xwhS9WNfMApFYxCix89kvKOcVo8T7j3vZQKp4BbQkOj6/ AkpwcLAIqEpsvZkAEmYT0JB4Om07I4jNL6AoMaP1BVi5qICfxNm57xghWgUlfky+xwJiiwi4 SXy++5sJZAyzgLFE57F6kLAwUPm0M1+g1nYzSiw9dArsOE4Bb4m1jf/BbGYBHYn9rdPYIGx5 ic1r3jKD2CwCAhLfJh8CO01CQFZi0wFmkDkSAvPYJY6/uQn1vaTEwRU3WCYwis9CctIsJGNn IRm7gJF5FaNoakFyQXFSeq6RXnFibnFpXrpecn7uJkZI3EjvYFzVYHGIUYCDUYmHl/PXzQAh 1sSy4srcQ4wSHMxKIrzOH4FCvCmJlVWpRfnxRaU5qcWHGH2Arp3ILCWanA+M6bySeENjA2ND Q0tDM1NLUwMcwkrivM0eKQFCAumJJanZqakFqUUw45g4OKUaGCc1yAp+ncRgHV6Qd6/i3pFN 9n83dMiw2cjkuLcprD/8cOKKxqnV/deWm/KXMIU0XjrYHMO3sW5hY/xjkz93Wxm2th3PEtON aHNonKHRu4a1h99FsXeGFvt2tWednVIKqqqdmmzrvde22H9Ne51Q3rPchqs+b/aXI+a/mjM5 j4btjUh8EL5RiaU4I9FQi7moOBEAzUZwbcgCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrCIsWRmVeSWpSXmKPExsVy+t9jAd1pU28FGEz7JGTxcP1NFosph7+w ODB53Lm2hy2AMaqB0SYjNTEltUghNS85PyUzL91WyTs43jne1MzAUNfQ0sJcSSEvMTfVVsnF J0DXLTMHaLaSQlliTilQKCCxuFhJ3w7ThNAQN10LmMYIXd+QILgeIwM0kLCOMePA4W1sBb1y Ff3//rA3ME6Q7GLk5JAQMJF4sa6ZBcIWk7hwbz1bFyMXh5DAIkaJnc9+sUA4rxgl3n/cywZS xSugJdHx+RVQgoODRUBVYuvNBJAwm4CGxNNp2xlBbH4BRYkZrS/AykUF/CTOzn3HCNEqKPFj 8j2wZSICbhKf7/5mAhnDLGAs0XmsHiQsDFQ+7cwXqLXdjBJLD51iBUlwCnhLrG38D2YzC+hI 7G+dxgZhy0tsXvOWeQKj4CwkK2YhKZuFpGwBI/MqRtHUguSC4qT0XCO94sTc4tK8dL3k/NxN jOCofCa9g3FVg8UhRgEORiUeXs5fNwOEWBPLiitzDzFKcDArifA6fwQK8aYkVlalFuXHF5Xm pBYfYvQBBsZEZinR5HxgwsgriTc0NjEzsjQyMzYxNzbGIawkztvskRIgJJCeWJKanZpakFoE M46Jg1OqgVHgkPrvbelVW7Uq/X0VNXSCFu25uXHv9aK+HbtfttiUaV8vKEh6+7h/gqfTDpcr R/37+hivqa6RXL41l+nPjYtxRllXfh38pdXLN/VE4SflQg+OxLLKa8vubN8Yu+bcwkqT/9fd Ge+vE75S876v6lVnsrOsvsr8Dwff+nw49/7gmeTQBvGFKV1KLMUZiYZazEXFiQAJDrPw9wIA AA== X-CFilter-Loop: Reflected X-Gm-Message-State: ALoCoQmDW10Iwz7YZKDylNCgzKJcq5DSdQ/z0RLgPAc7cypqSDjqu5yxqsdIPbIsuN6ey78qGSxl From: Chander Kashyap This patch adds gpio structure for Exynos4x12. Signed-off-by: Chander Kashyap Signed-off-by: Minkyu Kang --- Changes since v2: - None arch/arm/include/asm/arch-exynos/gpio.h | 85 +++++++++++++++++++++++++++++++ 1 file changed, 85 insertions(+) diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h index 4db8fd6..cfe1024 100644 --- a/arch/arm/include/asm/arch-exynos/gpio.h +++ b/arch/arm/include/asm/arch-exynos/gpio.h @@ -79,6 +79,67 @@ struct exynos4_gpio_part3 { struct s5p_gpio_bank z; }; +struct exynos4x12_gpio_part1 { + struct s5p_gpio_bank a0; + struct s5p_gpio_bank a1; + struct s5p_gpio_bank b; + struct s5p_gpio_bank c0; + struct s5p_gpio_bank c1; + struct s5p_gpio_bank d0; + struct s5p_gpio_bank d1; + struct s5p_gpio_bank res1[0x5]; + struct s5p_gpio_bank f0; + struct s5p_gpio_bank f1; + struct s5p_gpio_bank f2; + struct s5p_gpio_bank f3; + struct s5p_gpio_bank res2[0x2]; + struct s5p_gpio_bank j0; + struct s5p_gpio_bank j1; +}; + +struct exynos4x12_gpio_part2 { + struct s5p_gpio_bank res1[0x2]; + struct s5p_gpio_bank k0; + struct s5p_gpio_bank k1; + struct s5p_gpio_bank k2; + struct s5p_gpio_bank k3; + struct s5p_gpio_bank l0; + struct s5p_gpio_bank l1; + struct s5p_gpio_bank l2; + struct s5p_gpio_bank y0; + struct s5p_gpio_bank y1; + struct s5p_gpio_bank y2; + struct s5p_gpio_bank y3; + struct s5p_gpio_bank y4; + struct s5p_gpio_bank y5; + struct s5p_gpio_bank y6; + struct s5p_gpio_bank res2[0x3]; + struct s5p_gpio_bank m0; + struct s5p_gpio_bank m1; + struct s5p_gpio_bank m2; + struct s5p_gpio_bank m3; + struct s5p_gpio_bank m4; + struct s5p_gpio_bank res3[0x48]; + struct s5p_gpio_bank x0; + struct s5p_gpio_bank x1; + struct s5p_gpio_bank x2; + struct s5p_gpio_bank x3; +}; + +struct exynos4x12_gpio_part3 { + struct s5p_gpio_bank z; +}; + +struct exynos4x12_gpio_part4 { + struct s5p_gpio_bank v0; + struct s5p_gpio_bank v1; + struct s5p_gpio_bank res1[0x1]; + struct s5p_gpio_bank v2; + struct s5p_gpio_bank v3; + struct s5p_gpio_bank res2[0x1]; + struct s5p_gpio_bank v4; +}; + struct exynos5_gpio_part1 { struct s5p_gpio_bank a0; struct s5p_gpio_bank a1; @@ -163,6 +224,30 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode); - EXYNOS4_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \ * GPIO_PER_BANK) + pin) + EXYNOS4_GPIO_PART1_MAX) +#define exynos4x12_gpio_part1_get_nr(bank, pin) \ + ((((((unsigned int) &(((struct exynos4x12_gpio_part1 *) \ + EXYNOS4X12_GPIO_PART1_BASE)->bank)) \ + - EXYNOS4X12_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \ + * GPIO_PER_BANK) + pin) + +#define EXYNOS4X12_GPIO_PART1_MAX ((sizeof(struct exynos4x12_gpio_part1) \ + / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK) + +#define exynos4x12_gpio_part2_get_nr(bank, pin) \ + (((((((unsigned int) &(((struct exynos4x12_gpio_part2 *) \ + EXYNOS4X12_GPIO_PART2_BASE)->bank)) \ + - EXYNOS4X12_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \ + * GPIO_PER_BANK) + pin) + EXYNOS4X12_GPIO_PART1_MAX) + +#define EXYNOS4X12_GPIO_PART2_MAX ((sizeof(struct exynos4x12_gpio_part2) \ + / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK) + +#define exynos4x12_gpio_part3_get_nr(bank, pin) \ + (((((((unsigned int) &(((struct exynos4x12_gpio_part3 *) \ + EXYNOS4X12_GPIO_PART3_BASE)->bank)) \ + - EXYNOS4X12_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \ + * GPIO_PER_BANK) + pin) + EXYNOS4X12_GPIO_PART2_MAX) + #define exynos5_gpio_part1_get_nr(bank, pin) \ ((((((unsigned int) &(((struct exynos5_gpio_part1 *) \ EXYNOS5_GPIO_PART1_BASE)->bank)) \