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[203.254.224.24]) by mx.google.com with ESMTP id tp3si25075979pbc.115.2012.12.25.22.13.41; Tue, 25 Dec 2012 22:13:42 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of mk7.kang@samsung.com designates 203.254.224.24 as permitted sender) client-ip=203.254.224.24; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of mk7.kang@samsung.com designates 203.254.224.24 as permitted sender) smtp.mail=mk7.kang@samsung.com Received: from epcpsbgm1.samsung.com (epcpsbgm1 [203.254.230.26]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MFM0063YJYDC0J0@mailout1.samsung.com>; Wed, 26 Dec 2012 15:13:41 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [203.254.230.46]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 32.40.01231.5959AD05; Wed, 26 Dec 2012 15:13:41 +0900 (KST) X-AuditID: cbfee61a-b7fa66d0000004cf-a1-50da9595f92f Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id F1.40.01231.4959AD05; Wed, 26 Dec 2012 15:13:40 +0900 (KST) Received: from [10.90.45.134] by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MFM00BEQJYSD210@mmp2.samsung.com>; Wed, 26 Dec 2012 15:13:40 +0900 (KST) Message-id: <50DA9594.6010306@samsung.com> Date: Wed, 26 Dec 2012 15:13:40 +0900 From: Minkyu Kang Organization: SAMSUNG ELECTRONICS User-Agent: Mozilla/5.0 (X11; Linux i686; rv:17.0) Gecko/17.0 Thunderbird/17.0 MIME-version: 1.0 To: Chander Kashyap , u-boot@lists.denx.de Cc: linaro-dev@lists.linaro.org, patches@linaro.org Subject: [PATCH v3 2/3] EXYNOS: EXYNOS4X12: Add clock structure for EXYNOS4X12 References: <1354875686-31703-1-git-send-email-chander.kashyap@linaro.org> <1354875686-31703-3-git-send-email-chander.kashyap@linaro.org> In-reply-to: <1354875686-31703-3-git-send-email-chander.kashyap@linaro.org> Content-type: text/plain; charset=ISO-8859-1 Content-transfer-encoding: 7bit DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrKIsWRmVeSWpSXmKPExsVy+t8zPd2pU28FGFw+zmrxcP1NFosph7+w ODB53Lm2hy2AMYrLJiU1J7MstUjfLoErY/OViawFp1wrFp5oZmtg/GvZxcjJISFgItE6fzUL hC0mceHeejYQW0hgGaPEo01lMDUPX11m72LkAopPZ5To+rWPFcJ5xSjx7EMPE0gVr4CWxMkN l1hBbBYBVYmGnh1gcTYBDYmn07Yzgtj8AooSM1pfgG0QFfCTODv3HSNEr6DEj8n3wK4QEXCT +Hz3N1AvBwezgLFE57F6kLCwgL9E28t5bBB7uxklpjybwAyS4BTwlvh4+T3YLmYBHYn9rdPY IGx5ic1r3jJD3CMg8W3yIRaQmRICshKbDjCDzJEQmMcusX7WD6jvJSUOrrjBMoFRfBaSk2Yh GTsLydgFjMyrGEVTC5ILipPScw31ihNzi0vz0vWS83M3MULiRmoH48oGi0OMAhyMSjy8G7/f DBBiTSwrrsw9xCjBwawkwuv8ESjEm5JYWZValB9fVJqTWnyI0Qfo2onMUqLJ+cCYziuJNzQ2 MDY0tDQ0M7U0NcAhrCTO2+yREiAkkJ5YkpqdmlqQWgQzjomDU6qBUVLb7Vmhwzz/j7zq7opN Lzd4u01ssLwybbvw7cKMe8/nHYyKCl7Dtt39kduk+ZJH2aO6dDx82tZ35kQ9MDymKur4IuxR uuPa2A22ctb/D8+IOROx9Ya/5N505mjzfywxm5sP32lSZd2Te4lDdFFezTExheUTihefvVqX 4TJTNMFylnjMt7DpSizFGYmGWsxFxYkAu/S0iMgCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrKIsWRmVeSWpSXmKPExsVy+t9jQd0pU28FGLyabmPxcP1NFosph7+w ODB53Lm2hy2AMaqB0SYjNTEltUghNS85PyUzL91WyTs43jne1MzAUNfQ0sJcSSEvMTfVVsnF J0DXLTMHaLaSQlliTilQKCCxuFhJ3w7ThNAQN10LmMYIXd+QILgeIwM0kLCOMWPzlYmsBadc KxaeaGZrYPxr2cXIySEhYCLx8NVldghbTOLCvfVsXYxcHEIC0xklun7tY4VwXjFKPPvQwwRS xSugJXFywyVWEJtFQFWioWcHWJxNQEPi6bTtjCA2v4CixIzWF2wgtqiAn8TZue8YIXoFJX5M vscCYosIuEl8vvsbqJeDg1nAWKLzWD1IWFjAX6Lt5TyoI7oZJaY8m8AMkuAU8Jb4ePk92C5m AR2J/a3T2CBseYnNa94yT2AUnIVkxSwkZbOQlC1gZF7FKJpakFxQnJSea6hXnJhbXJqXrpec n7uJERyXz6R2MK5ssDjEKMDBqMTDu/H7zQAh1sSy4srcQ4wSHMxKIrzOH4FCvCmJlVWpRfnx RaU5qcWHGH2AoTGRWUo0OR+YMvJK4g2NTcyMLI3MjE3MjY1xCCuJ8zZ7pAQICaQnlqRmp6YW pBbBjGPi4JRqYDwguuRz0tcgd87HhbN7ogqZSvctU/vY0rLRyFPywIyTnhuvbG299dX8UPYC /rs/bbkiWjt3Js95r1hz81H6pG2xKguPtwnpSRyQfSrPcXde4ZyFFUf19iXZOHjGR0yrZAzL 8f6981z1fPPZJYG6bNsyTa8IxselC57N4jzOtYaTRW2PRdx6ayWW4oxEQy3mouJEAArMZvD4 AgAA X-CFilter-Loop: Reflected X-Gm-Message-State: ALoCoQlfwhNCFrEZaKHAldvaeFMdPeK/YYaMnCOTtnRXzS2uIgsfx2jAxLwtc502F+TnpUcXtsgK From: Chander Kashyap This patch adds clock structure for Exynos4x12. Signed-off-by: Chander Kashyap Signed-off-by: Minkyu Kang --- Changes since v2: - None arch/arm/include/asm/arch-exynos/clock.h | 276 ++++++++++++++++++++++++++++++ 1 file changed, 276 insertions(+) diff --git a/arch/arm/include/asm/arch-exynos/clock.h b/arch/arm/include/asm/arch-exynos/clock.h index ff6781a..9b56b4e 100644 --- a/arch/arm/include/asm/arch-exynos/clock.h +++ b/arch/arm/include/asm/arch-exynos/clock.h @@ -251,6 +251,282 @@ struct exynos4_clock { unsigned int div_iem_l1; }; +struct exynos4x12_clock { + unsigned char res1[0x4200]; + unsigned int src_leftbus; + unsigned char res2[0x1fc]; + unsigned int mux_stat_leftbus; + unsigned char res3[0xfc]; + unsigned int div_leftbus; + unsigned char res4[0xfc]; + unsigned int div_stat_leftbus; + unsigned char res5[0x1fc]; + unsigned int gate_ip_leftbus; + unsigned char res6[0x12c]; + unsigned int gate_ip_image; + unsigned char res7[0xcc]; + unsigned int clkout_leftbus; + unsigned int clkout_leftbus_div_stat; + unsigned char res8[0x37f8]; + unsigned int src_rightbus; + unsigned char res9[0x1fc]; + unsigned int mux_stat_rightbus; + unsigned char res10[0xfc]; + unsigned int div_rightbus; + unsigned char res11[0xfc]; + unsigned int div_stat_rightbus; + unsigned char res12[0x1fc]; + unsigned int gate_ip_rightbus; + unsigned char res13[0x15c]; + unsigned int gate_ip_perir; + unsigned char res14[0x9c]; + unsigned int clkout_rightbus; + unsigned int clkout_rightbus_div_stat; + unsigned char res15[0x3608]; + unsigned int epll_lock; + unsigned char res16[0xc]; + unsigned int vpll_lock; + unsigned char res17[0xec]; + unsigned int epll_con0; + unsigned int epll_con1; + unsigned int epll_con2; + unsigned char res18[0x4]; + unsigned int vpll_con0; + unsigned int vpll_con1; + unsigned int vpll_con2; + unsigned char res19[0xe4]; + unsigned int src_top0; + unsigned int src_top1; + unsigned char res20[0x8]; + unsigned int src_cam; + unsigned int src_tv; + unsigned int src_mfc; + unsigned int src_g3d; + unsigned char res21[0x4]; + unsigned int src_lcd; + unsigned int src_isp; + unsigned int src_maudio; + unsigned int src_fsys; + unsigned char res22[0xc]; + unsigned int src_peril0; + unsigned int src_peril1; + unsigned int src_cam1; + unsigned char res23[0xb4]; + unsigned int src_mask_top; + unsigned char res24[0xc]; + unsigned int src_mask_cam; + unsigned int src_mask_tv; + unsigned char res25[0xc]; + unsigned int src_mask_lcd; + unsigned int src_mask_isp; + unsigned int src_mask_maudio; + unsigned int src_mask_fsys; + unsigned char res26[0xc]; + unsigned int src_mask_peril0; + unsigned int src_mask_peril1; + unsigned char res27[0xb8]; + unsigned int mux_stat_top0; + unsigned int mux_stat_top1; + unsigned char res28[0x10]; + unsigned int mux_stat_mfc; + unsigned int mux_stat_g3d; + unsigned char res29[0x28]; + unsigned int mux_stat_cam1; + unsigned char res30[0xb4]; + unsigned int div_top; + unsigned char res31[0xc]; + unsigned int div_cam; + unsigned int div_tv; + unsigned int div_mfc; + unsigned int div_g3d; + unsigned char res32[0x4]; + unsigned int div_lcd; + unsigned int div_isp; + unsigned int div_maudio; + unsigned int div_fsys0; + unsigned int div_fsys1; + unsigned int div_fsys2; + unsigned int div_fsys3; + unsigned int div_peril0; + unsigned int div_peril1; + unsigned int div_peril2; + unsigned int div_peril3; + unsigned int div_peril4; + unsigned int div_peril5; + unsigned int div_cam1; + unsigned char res33[0x14]; + unsigned int div2_ratio; + unsigned char res34[0x8c]; + unsigned int div_stat_top; + unsigned char res35[0xc]; + unsigned int div_stat_cam; + unsigned int div_stat_tv; + unsigned int div_stat_mfc; + unsigned int div_stat_g3d; + unsigned char res36[0x4]; + unsigned int div_stat_lcd; + unsigned int div_stat_isp; + unsigned int div_stat_maudio; + unsigned int div_stat_fsys0; + unsigned int div_stat_fsys1; + unsigned int div_stat_fsys2; + unsigned int div_stat_fsys3; + unsigned int div_stat_peril0; + unsigned int div_stat_peril1; + unsigned int div_stat_peril2; + unsigned int div_stat_peril3; + unsigned int div_stat_peril4; + unsigned int div_stat_peril5; + unsigned int div_stat_cam1; + unsigned char res37[0x14]; + unsigned int div2_stat; + unsigned char res38[0x29c]; + unsigned int gate_ip_cam; + unsigned int gate_ip_tv; + unsigned int gate_ip_mfc; + unsigned int gate_ip_g3d; + unsigned char res39[0x4]; + unsigned int gate_ip_lcd; + unsigned int gate_ip_isp; + unsigned char res40[0x4]; + unsigned int gate_ip_fsys; + unsigned char res41[0x8]; + unsigned int gate_ip_gps; + unsigned int gate_ip_peril; + unsigned char res42[0xc]; + unsigned char res43[0x4]; + unsigned char res44[0xc]; + unsigned int gate_block; + unsigned char res45[0x8c]; + unsigned int clkout_cmu_top; + unsigned int clkout_cmu_top_div_stat; + unsigned char res46[0x3600]; + unsigned int mpll_lock; + unsigned char res47[0xfc]; + unsigned int mpll_con0; + unsigned int mpll_con1; + unsigned char res48[0xf0]; + unsigned int src_dmc; + unsigned char res49[0xfc]; + unsigned int src_mask_dmc; + unsigned char res50[0xfc]; + unsigned int mux_stat_dmc; + unsigned char res51[0xfc]; + unsigned int div_dmc0; + unsigned int div_dmc1; + unsigned char res52[0xf8]; + unsigned int div_stat_dmc0; + unsigned int div_stat_dmc1; + unsigned char res53[0xf8]; + unsigned int gate_bus_dmc0; + unsigned int gate_bus_dmc1; + unsigned char res54[0x1f8]; + unsigned int gate_ip_dmc0; + unsigned int gate_ip_dmc1; + unsigned char res55[0xf8]; + unsigned int clkout_cmu_dmc; + unsigned int clkout_cmu_dmc_div_stat; + unsigned char res56[0x5f8]; + unsigned int dcgidx_map0; + unsigned int dcgidx_map1; + unsigned int dcgidx_map2; + unsigned char res57[0x14]; + unsigned int dcgperf_map0; + unsigned int dcgperf_map1; + unsigned char res58[0x18]; + unsigned int dvcidx_map; + unsigned char res59[0x1c]; + unsigned int freq_cpu; + unsigned int freq_dpm; + unsigned char res60[0x18]; + unsigned int dvsemclk_en; + unsigned int maxperf; + unsigned char res61[0x8]; + unsigned int dmc_freq_ctrl; + unsigned int dmc_pause_ctrl; + unsigned int dddrphy_lock_ctrl; + unsigned int c2c_state; + unsigned char res62[0x2f60]; + unsigned int apll_lock; + unsigned char res63[0x8]; + unsigned char res64[0xf4]; + unsigned int apll_con0; + unsigned int apll_con1; + unsigned char res65[0xf8]; + unsigned int src_cpu; + unsigned char res66[0x1fc]; + unsigned int mux_stat_cpu; + unsigned char res67[0xfc]; + unsigned int div_cpu0; + unsigned int div_cpu1; + unsigned char res68[0xf8]; + unsigned int div_stat_cpu0; + unsigned int div_stat_cpu1; + unsigned char res69[0x2f8]; + unsigned int clk_gate_ip_cpu; + unsigned char res70[0xfc]; + unsigned int clkout_cmu_cpu; + unsigned int clkout_cmu_cpu_div_stat; + unsigned char res71[0x5f8]; + unsigned int armclk_stopctrl; + unsigned int atclk_stopctrl; + unsigned char res72[0x10]; + unsigned char res73[0x8]; + unsigned int pwr_ctrl; + unsigned int pwr_ctrl2; + unsigned char res74[0xd8]; + unsigned int apll_con0_l8; + unsigned int apll_con0_l7; + unsigned int apll_con0_l6; + unsigned int apll_con0_l5; + unsigned int apll_con0_l4; + unsigned int apll_con0_l3; + unsigned int apll_con0_l2; + unsigned int apll_con0_l1; + unsigned int iem_control; + unsigned char res75[0xdc]; + unsigned int apll_con1_l8; + unsigned int apll_con1_l7; + unsigned int apll_con1_l6; + unsigned int apll_con1_l5; + unsigned int apll_con1_l4; + unsigned int apll_con1_l3; + unsigned int apll_con1_l2; + unsigned int apll_con1_l1; + unsigned char res76[0xe0]; + unsigned int div_iem_l8; + unsigned int div_iem_l7; + unsigned int div_iem_l6; + unsigned int div_iem_l5; + unsigned int div_iem_l4; + unsigned int div_iem_l3; + unsigned int div_iem_l2; + unsigned int div_iem_l1; + unsigned char res77[0xe0]; + unsigned int l2_status; + unsigned char res78[0xc]; + unsigned int cpu_status; + unsigned char res79[0xc]; + unsigned int ptm_status; + unsigned char res80[0x2edc]; + unsigned int div_isp0; + unsigned int div_isp1; + unsigned char res81[0xf8]; + unsigned int div_stat_isp0; + unsigned int div_stat_isp1; + unsigned char res82[0x3f8]; + unsigned int gate_ip_isp0; + unsigned int gate_ip_isp1; + unsigned char res83[0x1f8]; + unsigned int clkout_cmu_isp; + unsigned int clkout_cmu_ispd_div_stat; + unsigned char res84[0xf8]; + unsigned int cmu_isp_spar0; + unsigned int cmu_isp_spar1; + unsigned int cmu_isp_spar2; + unsigned int cmu_isp_spar3; +}; + struct exynos5_clock { unsigned int apll_lock; unsigned char res1[0xfc];