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[203.254.224.24]) by mx.google.com with ESMTP id m9si8610311pav.309.2012.12.25.22.13.39; Tue, 25 Dec 2012 22:13:40 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of mk7.kang@samsung.com designates 203.254.224.24 as permitted sender) client-ip=203.254.224.24; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of mk7.kang@samsung.com designates 203.254.224.24 as permitted sender) smtp.mail=mk7.kang@samsung.com Received: from epcpsbgm2.samsung.com (epcpsbgm2 [203.254.230.27]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MFM00AI5JYN49G0@mailout1.samsung.com>; Wed, 26 Dec 2012 15:13:38 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [203.254.230.44]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 50.49.12699.2959AD05; Wed, 26 Dec 2012 15:13:38 +0900 (KST) X-AuditID: cbfee61b-b7f616d00000319b-01-50da9592a9f6 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 00.49.12699.2959AD05; Wed, 26 Dec 2012 15:13:38 +0900 (KST) Received: from [10.90.45.134] by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MFM00DVHJYQDU00@mmp1.samsung.com>; Wed, 26 Dec 2012 15:13:38 +0900 (KST) Message-id: <50DA9592.90301@samsung.com> Date: Wed, 26 Dec 2012 15:13:38 +0900 From: Minkyu Kang Organization: SAMSUNG ELECTRONICS User-Agent: Mozilla/5.0 (X11; Linux i686; rv:17.0) Gecko/17.0 Thunderbird/17.0 MIME-version: 1.0 To: Chander Kashyap , u-boot@lists.denx.de Cc: linaro-dev@lists.linaro.org, patches@linaro.org Subject: [PATCH v3 1/3] EXYNOS: EXYNOS4X12: Populate Exynos4x12 register addresses References: <1354875686-31703-1-git-send-email-chander.kashyap@linaro.org> <1354875686-31703-2-git-send-email-chander.kashyap@linaro.org> In-reply-to: <1354875686-31703-2-git-send-email-chander.kashyap@linaro.org> Content-type: text/plain; charset=ISO-8859-1 Content-transfer-encoding: 7bit DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrCIsWRmVeSWpSXmKPExsVy+t8zHd1JU28FGBz9q2fxcP1NFosph7+w ODB53Lm2hy2AMYrLJiU1J7MstUjfLoEro+dUM1PBacmKNQdamBoYN4h2MXJwSAiYSJzaH9nF yAlkiklcuLeerYuRi0NIYBmjxKfjX9khEiYSDydPYYdILGKU+HKxCcp5xSjxZsYrVpAqXgEN iYU7HrOB2CwCqhKX208wg9hsQPGn07Yzgtj8AooSM1pfgNWICvhJnJ37jhGiV1Dix+R7LCC2 iICbxOe7v5lArmMWMJboPFYPEhYWCJX4tegUWKuQQDejxKZr/CA2p4C3xNemQ2CtzAI6Evtb p7FB2PISm9e8ZYY4R0Di22SQGpCHZSU2HWAGOV9CYBG7xPsrc6CelJQ4uOIGywRG8VlILpqF ZOwsJGMXMDKvYhRNLUguKE5KzzXSK07MLS7NS9dLzs/dxAiJGukdjKsaLA4xCnAwKvHwcv66 GSDEmlhWXJl7iFGCg1lJhNf5I1CINyWxsiq1KD++qDQntfgQow/QtROZpUST84ERnVcSb2hs YGxoaGloZmppaoBDWEmct9kjJUBIID2xJDU7NbUgtQhmHBMHp1QDY4Lex54TKnIm+3O3uGjc zVod3HRXontdo8I5Z18hJf9+WxWthqWLqj7l3L7kUfJ178pf27T1dzMqfwnqcdycXK5REljS HXEo27Z95v5pXpfSzAQmbkyeHevOor06YYXQ8VDh91Hvt+w5uv7nO0ev4izGpfPeHVnE8JH9 yPz+hTG3eK68+l6vr8RSnJFoqMVcVJwIADBcojfHAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrCIsWRmVeSWpSXmKPExsVy+t9jAd1JU28FGGxt1bR4uP4mi8WUw19Y HJg87lzbwxbAGNXAaJORmpiSWqSQmpecn5KZl26r5B0c7xxvamZgqGtoaWGupJCXmJtqq+Ti E6DrlpkDNFtJoSwxpxQoFJBYXKykb4dpQmiIm64FTGOErm9IEFyPkQEaSFjHmNFzqpmp4LRk xZoDLUwNjBtEuxg5OSQETCQeTp7CDmGLSVy4t56ti5GLQ0hgEaPEl4tN7BDOK0aJNzNesYJU 8QpoSCzc8ZgNxGYRUJW43H6CGcRmA4o/nbadEcTmF1CUmNH6AqxGVMBP4uzcd4wQvYISPybf YwGxRQTcJD7f/c3UxcjBwSxgLNF5rB4kLCwQKvFr0SmwViGBbkaJTdf4QWxOAW+Jr02HwFqZ BXQk9rdOY4Ow5SU2r3nLPIFRcBaSDbOQlM1CUraAkXkVo2hqQXJBcVJ6rpFecWJucWleul5y fu4mRnBUPpPewbiqweIQowAHoxIPL+evmwFCrIllxZW5hxglOJiVRHidPwKFeFMSK6tSi/Lj i0pzUosPMfoAA2Mis5Rocj4wYeSVxBsam5gZWRqZGZuYGxvjEFYS5232SAkQEkhPLEnNTk0t SC2CGcfEwSnVwMh1Iv4Llzhf4+yAnTEZyX03PJvvP/uVHrNo0dLw1YLzVpZMeH9C/ovcPo3X MkfW9Sqvjd87P+wWz6nEhCCudT3fdNbtuXkm79GXszx/n1ZaR1YUHPTtW3dW8MZm1eaJEsed nucfurTpRG7DyVeCM9Z4/fCtyDxbYuUya/ausztmfPDnEss9lLhGiaU4I9FQi7moOBEAgrDn q/cCAAA= X-CFilter-Loop: Reflected X-Gm-Message-State: ALoCoQkHp08/RHvhCsfnkNZq98TPPFM6XalMWKt6XKTimmo6RYLWTvLLl+c0DtS6TIJSBWhVKVko From: Chander Kashyap This patch populates base addresses of Exynos4x12 registers. Signed-off-by: Chander Kashyap Signed-off-by: Minkyu Kang --- Changes since v2: - rebased, add SPI and I2S addresses. arch/arm/include/asm/arch-exynos/cpu.h | 48 ++++++++++++++++++++++++++++---- 1 file changed, 42 insertions(+), 6 deletions(-) diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h index f06af2e..eb34422 100644 --- a/arch/arm/include/asm/arch-exynos/cpu.h +++ b/arch/arm/include/asm/arch-exynos/cpu.h @@ -27,7 +27,7 @@ #define EXYNOS_CPU_NAME "Exynos" #define EXYNOS4_ADDR_BASE 0x10000000 -/* EXYNOS4 */ +/* EXYNOS4 Common*/ #define EXYNOS4_I2C_SPACING 0x10000 #define EXYNOS4_GPIO_PART3_BASE 0x03860000 @@ -63,7 +63,40 @@ #define EXYNOS4_DP_BASE DEVICE_NOT_AVAILABLE #define EXYNOS4_SPI_ISP_BASE DEVICE_NOT_AVAILABLE -/* EXYNOS5 */ +/* EXYNOS4X12 */ +#define EXYNOS4X12_GPIO_PART3_BASE 0x03860000 +#define EXYNOS4X12_PRO_ID 0x10000000 +#define EXYNOS4X12_SYSREG_BASE 0x10010000 +#define EXYNOS4X12_POWER_BASE 0x10020000 +#define EXYNOS4X12_SWRESET 0x10020400 +#define EXYNOS4X12_USBPHY_CONTROL 0x10020704 +#define EXYNOS4X12_CLOCK_BASE 0x10030000 +#define EXYNOS4X12_SYSTIMER_BASE 0x10050000 +#define EXYNOS4X12_WATCHDOG_BASE 0x10060000 +#define EXYNOS4X12_DMC0_BASE 0x10600000 +#define EXYNOS4X12_DMC1_BASE 0x10610000 +#define EXYNOS4X12_GPIO_PART4_BASE 0x106E0000 +#define EXYNOS4X12_GPIO_PART2_BASE 0x11000000 +#define EXYNOS4X12_GPIO_PART1_BASE 0x11400000 +#define EXYNOS4X12_FIMD_BASE 0x11C00000 +#define EXYNOS4X12_MIPI_DSIM_BASE 0x11C80000 +#define EXYNOS4X12_USBOTG_BASE 0x12480000 +#define EXYNOS4X12_MMC_BASE 0x12510000 +#define EXYNOS4X12_SROMC_BASE 0x12570000 +#define EXYNOS4X12_USB_HOST_EHCI_BASE 0x12580000 +#define EXYNOS4X12_USBPHY_BASE 0x125B0000 +#define EXYNOS4X12_UART_BASE 0x13800000 +#define EXYNOS4X12_I2C_BASE 0x13860000 +#define EXYNOS4X12_PWMTIMER_BASE 0x139D0000 + +#define EXYNOS4X12_ADC_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS4X12_DP_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS4X12_MODEM_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS4X12_I2S_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS4X12_SPI_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS4X12_SPI_ISP_BASE DEVICE_NOT_AVAILABLE + +/* EXYNOS5 Common*/ #define EXYNOS5_I2C_SPACING 0x10000 #define EXYNOS5_GPIO_PART4_BASE 0x03860000 @@ -154,17 +187,20 @@ static inline int proid_is_##type(void) \ } IS_EXYNOS_TYPE(exynos4210, 0x4210) +IS_EXYNOS_TYPE(exynos4412, 0x4412) IS_EXYNOS_TYPE(exynos5250, 0x5250) #define SAMSUNG_BASE(device, base) \ static inline unsigned int samsung_get_base_##device(void) \ { \ - if (cpu_is_exynos4()) \ + if (cpu_is_exynos4()) { \ + if (proid_is_exynos4412()) \ + return EXYNOS4X12_##base; \ return EXYNOS4_##base; \ - else if (cpu_is_exynos5()) \ + } else if (cpu_is_exynos5()) { \ return EXYNOS5_##base; \ - else \ - return 0; \ + } \ + return 0; \ } SAMSUNG_BASE(adc, ADC_BASE)