From patchwork Tue Feb 18 12:20:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Simek X-Patchwork-Id: 236492 List-Id: U-Boot discussion From: michal.simek at xilinx.com (Michal Simek) Date: Tue, 18 Feb 2020 13:20:37 +0100 Subject: [PATCH 07/16] arm64: zynqmp: Sync zynqmp fpga manager with mainline In-Reply-To: References: Message-ID: <3c1a0da3a0acac89daa7bc039d8b617f5a773558.1582028304.git.michal.simek@xilinx.com> From: Nava kishore Manne Sync zynqmp fpga manager with mainline. Signed-off-by: Nava kishore Manne Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-clk-ccf.dtsi | 4 ++++ arch/arm/dts/zynqmp.dtsi | 12 +++++++----- 2 files changed, 11 insertions(+), 5 deletions(-) diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi index 1098e890192c..0b0fb6e98788 100644 --- a/arch/arm/dts/zynqmp-clk-ccf.dtsi +++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi @@ -291,3 +291,7 @@ &xlnx_dp_snd_codec0 { clocks = <&zynqmp_clk DP_AUDIO_REF>; }; + +&zynqmp_pcap { + clocks = <&zynqmp_clk PCAP>; +}; diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index ec0dd73e1504..58ac62c4f851 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -149,6 +149,11 @@ #power-domain-cells = <0x1>; u-boot,dm-pre-reloc; + zynqmp_pcap: pcap { + compatible = "xlnx,zynqmp-pcap-fpga"; + clock-names = "ref_clk"; + }; + zynqmp_power: zynqmp-power { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-power"; @@ -180,9 +185,10 @@ fpga_full: fpga-full { compatible = "fpga-region"; - fpga-mgr = <&pcap>; + fpga-mgr = <&zynqmp_pcap>; #address-cells = <2>; #size-cells = <2>; + ranges; }; nvmem_firmware { @@ -195,10 +201,6 @@ }; }; - pcap: pcap { - compatible = "xlnx,zynqmp-pcap-fpga"; - }; - rst: reset-controller { compatible = "xlnx,zynqmp-reset"; #reset-cells = <1>;