From patchwork Thu Jan 16 07:54:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Simek X-Patchwork-Id: 239640 List-Id: U-Boot discussion From: michal.simek at xilinx.com (Michal Simek) Date: Thu, 16 Jan 2020 08:54:39 +0100 Subject: [PATCH] net: zynq_gem: Use ulong instead of u32 data type Message-ID: <302a03b42a9bc997db7c4e473bac404fa79fd8dc.1579161277.git.michal.simek@xilinx.com> From: T Karthik Reddy flush_dcache_range() expects unsigned long in the arguments. Here u32 variable is unable to hold the higher address value when ddr mapped to higher addresses & flushing lower address dchache range instead which is unmapped causing to crash. Signed-off-by: T Karthik Reddy Signed-off-by: Michal Simek --- drivers/net/zynq_gem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index c3fe8e3c563f..879129653df3 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -653,7 +653,7 @@ static int zynq_gem_probe(struct udevice *dev) return -ENOMEM; memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN); - u32 addr = (ulong)priv->rxbuffers; + ulong addr = (ulong)priv->rxbuffers; flush_dcache_range(addr, addr + roundup(RX_BUF * PKTSIZE_ALIGN, ARCH_DMA_MINALIGN)); barrier();