From patchwork Wed Jan 15 22:53:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Anderson X-Patchwork-Id: 239629 List-Id: U-Boot discussion From: seanga2 at gmail.com (Sean Anderson) Date: Wed, 15 Jan 2020 17:53:48 -0500 Subject: [PATCH v2 05/11] riscv: Add option to disable writes to mcounteren In-Reply-To: <3411d84b-5a56-ae4e-1deb-085ef1a4971d@gmail.com> References: <3411d84b-5a56-ae4e-1deb-085ef1a4971d@gmail.com> Message-ID: <2eef694b-a166-3d62-bfab-a39e87cecf0a@gmail.com> On the kendryte k210, writes to mcounteren result in an illegal instruction exception. Signed-off-by: Sean Anderson --- Changes for v2: Moved forward in the patch series arch/riscv/Kconfig | 3 +++ arch/riscv/cpu/cpu.c | 2 ++ 2 files changed, 5 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 9a7b0334c2..4f8c62dcff 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -226,6 +226,9 @@ config XIP from a NOR flash memory without copying the code to ram. Say yes here if U-Boot boots from flash directly. +config SYS_RISCV_NOCOUNTER + bool "Disable accesses to the mcounteren CSR" + config STACK_SIZE_SHIFT int default 14 diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index e457f6acbf..df9eae663c 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -89,7 +89,9 @@ int arch_cpu_init_dm(void) * Enable perf counters for cycle, time, * and instret counters only */ +#ifndef CONFIG_SYS_RISCV_NOCOUNTER csr_write(CSR_MCOUNTEREN, GENMASK(2, 0)); +#endif /* Disable paging */ if (supports_extension('s'))