From patchwork Tue May 12 06:48:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Simek X-Patchwork-Id: 245620 List-Id: U-Boot discussion From: michal.simek at xilinx.com (Michal Simek) Date: Tue, 12 May 2020 08:48:28 +0200 Subject: [PATCH 3/5] fpga: zynqpl: Check if aes engine is enabled In-Reply-To: References: Message-ID: <203ffd1c3730bd2abc3c28cfc6fcbf10480cc198.1589266106.git.michal.simek@xilinx.com> From: Ibai Erkiaga AES engine cannot be used if has not been enabled at boot time with an encrypted boot image. Signed-off-by: Ibai Erkiaga Acked-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- drivers/fpga/zynqpl.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c index 3f3c97e144cd..a323733ef363 100644 --- a/drivers/fpga/zynqpl.c +++ b/drivers/fpga/zynqpl.c @@ -19,6 +19,7 @@ #define DEVCFG_CTRL_PCFG_PROG_B 0x40000000 #define DEVCFG_CTRL_PCFG_AES_EFUSE_MASK 0x00001000 #define DEVCFG_CTRL_PCAP_RATE_EN_MASK 0x02000000 +#define DEVCFG_CTRL_PCFG_AES_EN_MASK 0x00000E00 #define DEVCFG_ISR_FATAL_ERROR_MASK 0x00740040 #define DEVCFG_ISR_ERROR_FLAGS_MASK 0x00340840 #define DEVCFG_ISR_RX_FIFO_OV 0x00040000 @@ -519,6 +520,13 @@ int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen, return FPGA_FAIL; } + /* Check AES engine is enabled */ + if (!(readl(&devcfg_base->ctrl) & + DEVCFG_CTRL_PCFG_AES_EN_MASK)) { + printf("%s: AES engine is not enabled\n", __func__); + return FPGA_FAIL; + } + if (zynq_dma_xfer_init(bstype)) { printf("%s: zynq_dma_xfer_init FAIL\n", __func__); return FPGA_FAIL;