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[176.92.181.30]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438dcc6df2asm48076345e9.29.2025.01.29.23.21.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Jan 2025 23:21:14 -0800 (PST) From: Ilias Apalodimas To: maz@kernel.org, trini@konsulko.com, CFSworks@gmail.com Cc: Ilias Apalodimas , Caleb Connolly , Neil Armstrong , Sumit Garg , Heinrich Schuchardt , Simon Glass , Marek Vasut , Peter Robinson , =?utf-8?q?Pierre-Cl=C3=A9ment_Tosi?= , Sam Protsenko , Sughosh Ganu , Peng Fan , Richard Henderson , Andre Przywara , Peter Hoyes , Patrick Rudolph , Sam Day , Evgeny Bachinin , Jerome Forissier , Michal Simek , Christian Marangi , u-boot@lists.denx.de, u-boot-qcom@groups.io Subject: [RFC PATCH 1/4] meminfo: add memory details for armv8 Date: Thu, 30 Jan 2025 09:20:26 +0200 Message-ID: <20250130072100.27297-2-ilias.apalodimas@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250130072100.27297-1-ilias.apalodimas@linaro.org> References: <20250130072100.27297-1-ilias.apalodimas@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Upcoming patches are mapping memory with RO, RW^X etc permsissions. Fix the meminfo command to display them properly Signed-off-by: Ilias Apalodimas Acked-by: Jerome Forissier --- arch/arm/cpu/armv8/cache_v8.c | 18 +++++++++++++++++- arch/arm/include/asm/armv8/mmu.h | 2 ++ cmd/meminfo.c | 5 +++++ 3 files changed, 24 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 5d6953ffedd1..a4ca56c8ed42 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -421,7 +421,7 @@ static int count_ranges(void) return count; } -#define ALL_ATTRS (3 << 8 | PMD_ATTRINDX_MASK) +#define ALL_ATTRS (3 << 8 | PMD_ATTRMASK) #define PTE_IS_TABLE(pte, level) (pte_type(&(pte)) == PTE_TYPE_TABLE && (level) < 3) enum walker_state { @@ -568,6 +568,17 @@ static void pretty_print_table_attrs(u64 pte) static void pretty_print_block_attrs(u64 pte) { u64 attrs = pte & PMD_ATTRINDX_MASK; + u64 perm_attrs = pte & PMD_ATTRMASK; + + if ((perm_attrs & PTE_BLOCK_PXN) && (perm_attrs & PTE_BLOCK_UXN) && + perm_attrs & PTE_BLOCK_RO) + printf("%-5s", " | RO"); + else if ((perm_attrs & PTE_BLOCK_PXN) && (perm_attrs & PTE_BLOCK_UXN)) + printf("%-5s", " | RW"); + else if (perm_attrs & PTE_BLOCK_RO) + printf("%-5s", " | RX"); + else + printf("%-5s", " | RWX"); switch (attrs) { case PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE): @@ -1112,3 +1123,8 @@ void __weak enable_caches(void) icache_enable(); dcache_enable(); } + +void arch_dump_mem_attrs(void) +{ + dump_pagetable(gd->arch.tlb_addr, get_tcr(NULL, NULL)); +} diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index 0ab681c893d3..6af8cd111a44 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -66,6 +66,7 @@ #define PTE_BLOCK_NG (1 << 11) #define PTE_BLOCK_PXN (UL(1) << 53) #define PTE_BLOCK_UXN (UL(1) << 54) +#define PTE_BLOCK_RO (UL(1) << 7) /* * AttrIndx[2:0] @@ -75,6 +76,7 @@ #define PMD_ATTRMASK (PTE_BLOCK_PXN | \ PTE_BLOCK_UXN | \ PMD_ATTRINDX_MASK | \ + PTE_BLOCK_RO | \ PTE_TYPE_VALID) /* diff --git a/cmd/meminfo.c b/cmd/meminfo.c index 5e83d61c2dd3..3915e2bbb268 100644 --- a/cmd/meminfo.c +++ b/cmd/meminfo.c @@ -15,6 +15,10 @@ DECLARE_GLOBAL_DATA_PTR; +void __weak arch_dump_mem_attrs(void) +{ +} + static void print_region(const char *name, ulong base, ulong size, ulong *uptop) { ulong end = base + size; @@ -54,6 +58,7 @@ static int do_meminfo(struct cmd_tbl *cmdtp, int flag, int argc, puts("DRAM: "); print_size(gd->ram_size, "\n"); + arch_dump_mem_attrs(); if (!IS_ENABLED(CONFIG_CMD_MEMINFO_MAP)) return 0;