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Mon, 25 Nov 2024 01:46:18 -0800 (PST) From: Neil Armstrong Date: Mon, 25 Nov 2024 10:46:16 +0100 Subject: [PATCH 1/2] pci: pcie_dw_common: introduce pcie_dw_find_capability() MIME-Version: 1.0 Message-Id: <20241125-topic-pcie-controller-v1-1-45c20070dd53@linaro.org> References: <20241125-topic-pcie-controller-v1-0-45c20070dd53@linaro.org> In-Reply-To: <20241125-topic-pcie-controller-v1-0-45c20070dd53@linaro.org> To: Tom Rini , Caleb Connolly , Sumit Garg Cc: u-boot@lists.denx.de, u-boot-qcom@groups.io, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2511; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=y2HdtS5CQGOYvcDh20iPQF5aU5NB6kPBpR2LOqM+p7k=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBnREdpTtvmZVEomk92F5J6fIzrbKn5MO98MSXXzXi2 uHwRGKCJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZ0RHaQAKCRB33NvayMhJ0fNIEA CtXqJKB6RHsdEL9nTmITSe6ppGHfAMqoPtKm6AHFRgj6IVeWVCNZPRSZb+4KSeo1imOLg9ayeTJ826 3CsQuKvIorAFdt4jLq0htf1MDPXnikDfNzxzmpnC3dxHWJcBR7aLW4cV+dtjI0AocFDeKmIeIppvUa JXe2tTJIMF5WRggSS0PMbaA4ffizA/Ae71FrgGb/cCz0Y3ZrLOevivoI8ZeIgG3/eec78wdQgiCIQl wWsDVLpMZn+KOJRD4Rb4wXzg8v6xd2JLTxHPSgXugKXqDAn5B66yiyV/JexAKK3Zxn2Icd35q2P+dQ sxv+jwquQb/VMeZlohrvSQV4/wN0UVNJrdt7CVZiVgHyhvVfXHyQ5OivMn8Y9CgDpNxCWNaEYeYR0g o1/26/UL4XYb7oqLUyb9bG5moo+8hYoErjtUABOpZOklWIl74XhM/v8FoxvmuEsQfOBo3Vg0V+M0I7 EUwT88AtNZxFyrBpwYyGuqsVpGpCVVce+d0PvEg++pEjHePchP+xWylLK6FZZSsYGsargzD+G3QTTG hlhA0FlctpjF8gQiO9NeN6eczqAPoofm2aC/RwAAHD3PlRn3qiuw/f6nLklazQQXnuvzIsoO6Waj2Q 2u95055rtwXAJBz+XStGJhuVVMSlwitsQNAJse2V9s6RoXY07/NYIZ7Io/+Q== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Add PCIe config space capability search function specific for the host controller, which are bridges *to* PCI devices but are not PCI devices themselves. Signed-off-by: Neil Armstrong --- drivers/pci/pcie_dw_common.c | 42 ++++++++++++++++++++++++++++++++++++++++++ drivers/pci/pcie_dw_common.h | 2 ++ 2 files changed, 44 insertions(+) diff --git a/drivers/pci/pcie_dw_common.c b/drivers/pci/pcie_dw_common.c index 0673e516c6fee6c01e5a5d23592e0ef55d49d823..78961271a8eef8e4b6991675ee9de2bb1968b8da 100644 --- a/drivers/pci/pcie_dw_common.c +++ b/drivers/pci/pcie_dw_common.c @@ -267,6 +267,48 @@ int pcie_dw_write_config(struct udevice *bus, pci_dev_t bdf, pcie->io.bus_start, pcie->io.size); } +/* + * These interfaces resemble the pci_find_*capability() interfaces, but these + * are for configuring host controllers, which are bridges *to* PCI devices but + * are not PCI devices themselves. + */ +static u8 pcie_dw_find_next_cap(struct pcie_dw *pci, u8 cap_ptr, u8 cap) +{ + u8 cap_id, next_cap_ptr; + u32 val; + u16 reg; + + if (!cap_ptr) + return 0; + + val = readl(pci->dbi_base + (cap_ptr & ~0x3)); + reg = pci_conv_32_to_size(val, cap_ptr, 2); + cap_id = (reg & 0x00ff); + + if (cap_id > PCI_CAP_ID_MAX) + return 0; + + if (cap_id == cap) + return cap_ptr; + + next_cap_ptr = (reg & 0xff00) >> 8; + return pcie_dw_find_next_cap(pci, next_cap_ptr, cap); +} + +u8 pcie_dw_find_capability(struct pcie_dw *pci, u8 cap) +{ + u8 next_cap_ptr; + u32 val; + u16 reg; + + val = readl(pci->dbi_base + (PCI_CAPABILITY_LIST & ~0x3)); + reg = pci_conv_32_to_size(val, PCI_CAPABILITY_LIST, 2); + + next_cap_ptr = (reg & 0x00ff); + + return pcie_dw_find_next_cap(pci, next_cap_ptr, cap); +} + /** * pcie_dw_setup_host() - Setup the PCIe controller for RC opertaion * diff --git a/drivers/pci/pcie_dw_common.h b/drivers/pci/pcie_dw_common.h index e0f7796f2a873f91ef74bc6ce84966a4215c22f0..8cb99a12ea1a5fd3687f980cc1ff99839d06dbc2 100644 --- a/drivers/pci/pcie_dw_common.h +++ b/drivers/pci/pcie_dw_common.h @@ -139,6 +139,8 @@ int pcie_dw_read_config(const struct udevice *bus, pci_dev_t bdf, uint offset, u int pcie_dw_write_config(struct udevice *bus, pci_dev_t bdf, uint offset, ulong value, enum pci_size_t size); +u8 pcie_dw_find_capability(struct pcie_dw *pci, u8 cap); + static inline void dw_pcie_dbi_write_enable(struct pcie_dw *pci, bool en) { u32 val;