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Wed, 02 Oct 2024 07:39:37 -0700 (PDT) From: Neil Armstrong Date: Wed, 02 Oct 2024 16:39:33 +0200 Subject: [PATCH v3 2/3] usb: dwc3: fix dcache flush range calculation MIME-Version: 1.0 Message-Id: <20241002-u-boot-dwc3-gadget-dcache-fixup-v3-2-5398088ef93c@linaro.org> References: <20241002-u-boot-dwc3-gadget-dcache-fixup-v3-0-5398088ef93c@linaro.org> In-Reply-To: <20241002-u-boot-dwc3-gadget-dcache-fixup-v3-0-5398088ef93c@linaro.org> To: Marek Vasut , Tom Rini , Lukasz Majewski , Mattijs Korpershoek , Bin Meng Cc: Caleb Connolly , u-boot-qcom@groups.io, u-boot@lists.denx.de, Neil Armstrong X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=1510; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=y5L/ah81b52wg2BmUIBDjC9IK51neBebBKPXX2bS1kY=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBm/VsncgLj8ZE6ED+Md4TtA91Kn2hdkE1XO7lhZWvK WjJbWUqJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZv1bJwAKCRB33NvayMhJ0XQOD/ 4zFItGtjvmgfMrc4tdNBqGcrgt3ca2zr57HvavxIadd8tHujqtoqxaWHHqCjIO0gvg+9fAC8lDmns2 6vCEmMsGJlLEtjztYRJGYQvRdcvqetzdwPAUGLdRWvM4TM22+m8DEFdP7fhAHbFVJFufvr+pAFQySc 2Kky04jHSJry+UhYSyTbQHPUTtXpCW7JGxlk7ScS8w0O5Y0bwRgdjk60eOICT66y3cRoZSoDErfIjb yLh3mzOZPYznEEyjfQSeq1Y7dSvedjuatxdXZtTf+LpHp/tBU/XMhtlO2d/fFL8RxDromOF3l25z0a 5pEQ93lGtnzeNZEpACPJ+W13n+YBlkIB3IljXCldt8+YN78fw1nWo0/lSt6JS+6GnmwsKKJPC1/lmM HOyRyVy4yilAf0iwkNEOoV6zwGale+3HXuOmBIJl9Ao++xFx1szK1jWTjoQAhMN5hdndptsG0SlgNU dgsDuXYK5UNRQC9G7buIjRRMcDyc/rqfnchmnei3w3R/06TbBYuXUXvTklNlUij+kEuILjv9c/e0VW 4lZE6c1Zll6TioiQQTBNCwaDTHHFfCQDlMvYkDTO+YFeA4BoauucBJgN1qMpwEI80/wZoPn+J0RE8m POM5wPmbnoT3pX4oGklZwqarSJTuI1e0xhnILhc3pzQrFSUrngHtLzdzcKnQ== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The current flush operation will omit doing a flush/invalidate on the first and last bytes if the base address and size are not aligned with DMA_MINALIGN. This causes operation failures Qualcomm platforms. Take in account the alignment and size of the buffer and also flush the previous and last cacheline. Remove CACHELINE_SIZE which was the same as DMA_MINALIGN. Reviewed-by: Mattijs Korpershoek Signed-off-by: Neil Armstrong --- drivers/usb/dwc3/io.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/usb/dwc3/io.h b/drivers/usb/dwc3/io.h index 04791d4c9be..a6c2bb0f47d 100644 --- a/drivers/usb/dwc3/io.h +++ b/drivers/usb/dwc3/io.h @@ -20,7 +20,6 @@ #include #include -#define CACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE static inline u32 dwc3_readl(void __iomem *base, u32 offset) { unsigned long offs = offset - DWC3_GLOBALS_REGS_START; @@ -50,6 +49,9 @@ static inline void dwc3_writel(void __iomem *base, u32 offset, u32 value) static inline void dwc3_flush_cache(uintptr_t addr, int length) { - flush_dcache_range(addr, addr + ROUND(length, CACHELINE_SIZE)); + uintptr_t start_addr = (uintptr_t)addr & ~(ARCH_DMA_MINALIGN - 1); + uintptr_t end_addr = ALIGN((uintptr_t)addr + length, ARCH_DMA_MINALIGN); + + flush_dcache_range((unsigned long)start_addr, (unsigned long)end_addr); } #endif /* __DRIVERS_USB_DWC3_IO_H */