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Mon, 30 Sep 2024 05:44:32 -0700 (PDT) From: Neil Armstrong Date: Mon, 30 Sep 2024 14:44:24 +0200 Subject: [PATCH v3 02/13] ufs: fix dcache flush and invalidate range calculation MIME-Version: 1.0 Message-Id: <20240930-topic-ufs-enhancements-v3-2-58234f84ab89@linaro.org> References: <20240930-topic-ufs-enhancements-v3-0-58234f84ab89@linaro.org> In-Reply-To: <20240930-topic-ufs-enhancements-v3-0-58234f84ab89@linaro.org> To: Tom Rini , Bhupesh Sharma , Neha Malcom Francis Cc: Michal Simek , Marek Vasut , bmeng.cn@gmail.com, u-boot@lists.denx.de, u-boot-qcom@groups.io, Neil Armstrong , Venkatesh Yadav Abbarapu X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=1993; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=1UTsvGfPS+P9xfQFHCxXJNZU4eiTF4UOb0MRc89nBcg=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBm+p0ofaIm8Xuxt0VG2M0ExY1lkNbsRTrfsjpORxaF Bk5iXpaJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZvqdKAAKCRB33NvayMhJ0f2cD/ 9oVv7RgRkGhvn8c/v1GcgOn/fZd+qi5c8r7bpF2EPdy5CGpD/zO4VdSHZcwEXRixN4AyDpKtSdQvbY xBEcu+rTw3FYFFG1ANvXGLqDnz+MdVNuVtPXZ2+u0vqSVn5h1FekCQTUNfj03w2MW99XJ1bn/cjM8a HX2gkNYDL09au4zlL1ejyvOq+tTNqM2VkxCUuko0zPBQ5v/UVGWEzLgrHskYT+wT6fsWhGMfU4WXDo dBpsafvwMJ/aeRWqmFUZOr7wg48Zhe55lveRpMJ4/tgtEbwyb/3KNu9ZoUM7uQgBb5M4zf8K/s7Sy7 1eNWsRvjEnxv9Q8pazmX2RBQjXaqQeibVGww3f5KLY0giRzxSQIpCDLluzl98lMJsuoPXFNP+K9P+e 0ahaeq3Gtbh5RMKGVLnNYE0PMyerfRjGZUeMKvz7IKlLIqM7vnvqaCe97yvkusyQeMM/AOODvGi7+Q BkAykO1J3B6U6yDTufIN7qwa8xx/5tbLZmFzzOTTH41HP9VOfR73r9Lor2kgOujoYUzDnRC1jROHSz yfJLbxu5BJaI9AYBwzEj/N8L2Wj64uiytkX5j9fpHq3KQ8XwPRY5eIAaOPNo1mWU0LgOeyDhIM4/IV 75wUGBEIXz624axCAVVEuoptRd9QyI5hKeZxbE1ghrpcgKrFmq3ioAqI1zkQ== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The current calculation will omit doing a flush/invalidate on the last cacheline if the base address is not aligned with DMA_MINALIGN. This causes commands failures and write corruptions on Qualcomm platforms. Reviewed-by: Neha Malcom Francis Tested-by: Venkatesh Yadav Abbarapu Signed-off-by: Neil Armstrong --- drivers/ufs/ufs.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/ufs/ufs.c b/drivers/ufs/ufs.c index e005cc90608..3d9a7d7ee12 100644 --- a/drivers/ufs/ufs.c +++ b/drivers/ufs/ufs.c @@ -703,11 +703,11 @@ static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba) */ static void ufshcd_cache_flush_and_invalidate(void *addr, unsigned long size) { - uintptr_t aaddr = (uintptr_t)addr & ~(ARCH_DMA_MINALIGN - 1); - unsigned long asize = ALIGN(size, ARCH_DMA_MINALIGN); + uintptr_t start_addr = (uintptr_t)addr & ~(ARCH_DMA_MINALIGN - 1); + uintptr_t end_addr = ALIGN((uintptr_t)addr + size, ARCH_DMA_MINALIGN); - flush_dcache_range(aaddr, aaddr + asize); - invalidate_dcache_range(aaddr, aaddr + asize); + flush_dcache_range(start_addr, end_addr); + invalidate_dcache_range(start_addr, end_addr); } /** @@ -1466,13 +1466,13 @@ static void prepare_prdt_table(struct ufs_hba *hba, struct scsi_cmd *pccb) } if (pccb->dma_dir == DMA_TO_DEVICE) { /* Write to device */ - flush_dcache_range(aaddr, aaddr + - ALIGN(datalen, ARCH_DMA_MINALIGN)); + flush_dcache_range(aaddr, + ALIGN((uintptr_t)pccb->pdata + datalen, ARCH_DMA_MINALIGN)); } /* In any case, invalidate cache to avoid stale data in it. */ - invalidate_dcache_range(aaddr, aaddr + - ALIGN(datalen, ARCH_DMA_MINALIGN)); + invalidate_dcache_range(aaddr, + ALIGN((uintptr_t)pccb->pdata + datalen, ARCH_DMA_MINALIGN)); table_length = DIV_ROUND_UP(pccb->datalen, MAX_PRDT_ENTRY); buf = pccb->pdata;