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[2a01:238:438b:c500:173d:9f52:ddab:ee01]) by mx.google.com with ESMTPS id 4fb4d7f45d1cf-5bec315f1dfsi7990342a12.653.2024.08.21.04.03.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Aug 2024 04:03:32 -0700 (PDT) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; Authentication-Results: mx.google.com; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 41EA188DE8; Wed, 21 Aug 2024 13:00:43 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id A3C0D88DE0; Wed, 21 Aug 2024 13:00:41 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.2 required=5.0 tests=BAYES_00, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED,RCVD_IN_VALIDITY_RPBL_BLOCKED, SPF_HELO_NONE,SPF_SOFTFAIL,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.2 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id 0F70188DF5 for ; Wed, 21 Aug 2024 13:00:39 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=fail smtp.mailfrom=sughosh.ganu@linaro.org Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 97919DA7; Wed, 21 Aug 2024 04:01:04 -0700 (PDT) Received: from a079122.blr.arm.com (a079122.arm.com [10.162.17.48]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 365F73F73B; Wed, 21 Aug 2024 04:00:34 -0700 (PDT) From: Sughosh Ganu To: u-boot@lists.denx.de Cc: Simon Glass , Tom Rini , Ilias Apalodimas , Heinrich Schuchardt , Marek Vasut , Mark Kettenis , Michal Simek , Patrick DELAUNAY , Patrice CHOTARD , Sughosh Ganu Subject: [PATCH v3 26/27] stm32mp: compute ram_top based on the optee base address Date: Wed, 21 Aug 2024 16:28:38 +0530 Message-Id: <20240821105839.2870293-27-sughosh.ganu@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240821105839.2870293-1-sughosh.ganu@linaro.org> References: <20240821105839.2870293-1-sughosh.ganu@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The value of ram_top address currently gets computed in an indirect manner. The boot_fdt_add_mem_rsv_regions() function gets called first to reserve the memory region occupied by OP-TEE in the LMB memory map. This is followed by a call to the lmb_alloc() API, which returns an address which is below the OP-TEE base address. This address is the value of ram_top returned by the board_get_usable_ram_top() function. This has now changed, as the LMB memory map, which is no longer local, gets set up after relocation. Get the OP-TEE base address by reading the device tree, and set the ram_top from this value. Signed-off-by: Sughosh Ganu --- Changes since V2: None arch/arm/mach-stm32mp/dram_init.c | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) diff --git a/arch/arm/mach-stm32mp/dram_init.c b/arch/arm/mach-stm32mp/dram_init.c index b3dbd521b7..32baefca71 100644 --- a/arch/arm/mach-stm32mp/dram_init.c +++ b/arch/arm/mach-stm32mp/dram_init.c @@ -62,8 +62,10 @@ int dram_init(void) phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { + int ret; phys_size_t size; phys_addr_t reg; + u32 optee_start, optee_size; if (!total_size) return gd->ram_top; @@ -73,16 +75,10 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size) * if the effective available memory is bigger */ gd->ram_top = clamp_val(gd->ram_top, 0, SZ_4G - 1); + size = ALIGN(SZ_8M + CONFIG_SYS_MALLOC_LEN + total_size, MMU_SECTION_SIZE); - /* found enough not-reserved memory to relocated U-Boot */ - lmb_add(gd->ram_base, gd->ram_top - gd->ram_base); - boot_fdt_add_mem_rsv_regions((void *)gd->fdt_blob); - /* add 8M for reserved memory for display, fdt, gd,... */ - size = ALIGN(SZ_8M + CONFIG_SYS_MALLOC_LEN + total_size, MMU_SECTION_SIZE), - reg = lmb_alloc(size, MMU_SECTION_SIZE); - - if (!reg) - reg = gd->ram_top - size; + ret = optee_get_reserved_memory(&optee_start, &optee_size); + reg = (!ret ? optee_start : gd->ram_top) - size; /* before relocation, mark the U-Boot memory as cacheable by default */ if (!(gd->flags & GD_FLG_RELOC))