From patchwork Wed Jul 24 06:02:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sughosh Ganu X-Patchwork-Id: 814143 Delivered-To: patch@linaro.org Received: by 2002:adf:f288:0:b0:367:895a:4699 with SMTP id k8csp2618847wro; Tue, 23 Jul 2024 23:08:05 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVSgr/JGcyRoB/jyut8yU8dmRCOcDVSZW6BOOkFXC4NOgTgq48D9DoG38xLSYjKjfo5cDDfE9h7qb1ozKrlQSXD X-Google-Smtp-Source: AGHT+IFo47z/nSD4WRyLtkgmbNxXfyBRBQBCZNXIdqX/s8Lrwp+QhpTzhaRT+SXKkHWzAzpLmRmm X-Received: by 2002:a05:6000:154d:b0:368:4e2e:7596 with SMTP id ffacd0b85a97d-369dec1e50cmr5069348f8f.37.1721801285546; Tue, 23 Jul 2024 23:08:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1721801285; cv=none; d=google.com; s=arc-20160816; b=tNE64Q+lRNV51BLrb3kRtV129yVsSHlazvE86ljtKolqn32Int1fhjXdeW8UVfZjGk 3nF5WYUo7E4Xh0FVyT/SDlHx//b1KV2FZfOuCeoY5h9RxIKd+xmCCQfj5fwEBQCYhtre fMHfnxyJT96UFFxwC3f3z25mO6jDVmBp7OND5BZ3TQ/fq0/5snOgyvCQ73RqRQjICIXl woE5y4fI8a7NI5R/ea68JGfs7fYoIy7aGLZ7YwQb8IhrsaiETBfvmKUFc/iqDTDhELYt +mTOa/fL6wena36lYE1WPWD6oLdA4L9/fQqhg2hinDlXPyB7Cy0YnSGNXscgt3J7xuQL xyCw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from; bh=RPPrx1eUj2am+uOAsjr1zfTZTTQSUDQRJQXMha3AlZw=; fh=eimiGswTlodK8yi2DcDfSicmKwvq5bxKQKpD+SkkTNY=; b=GvC5c5XKsY3BkOMMUShvqqgydl64J1ffsp6H9vNaFXF5FbhYvw1l+T3AbXV6T4zS92 xhoq8Uo6tuv8RwEHe9KeAdZWLhsBYWn3verylxT4MsfDXrLGj2YCZjWQuCn7lBPEyTPt x20wWgEgtltPHvHtSAxAU3jZg+u+Za3toMZ90LOjNH5l5tfiV1VHSiofrKpegMX1Y/xj KL2m4GgOIDgvmouEJuchGab+h/TtWg/T0WxFiJa3FVUObBaEgPfjVGIZgiQnoOR9U3rh 0hS6tEgvs28aQzak4r/6NBi0+Uon8ZRQZoqqIAasOaL5tc1fD7MNL5xePPF7AQDZ4gIz WOlw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [85.214.62.61]) by mx.google.com with ESMTPS id ffacd0b85a97d-369e365cd5asi1360436f8f.120.2024.07.23.23.08.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Jul 2024 23:08:05 -0700 (PDT) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) client-ip=85.214.62.61; Authentication-Results: mx.google.com; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id BAE6388852; Wed, 24 Jul 2024 08:04:31 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 1604A887CE; Wed, 24 Jul 2024 08:04:30 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.2 required=5.0 tests=BAYES_00, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED,RCVD_IN_VALIDITY_RPBL_BLOCKED, SPF_HELO_NONE,SPF_SOFTFAIL autolearn=no autolearn_force=no version=3.4.2 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id C3BA188907 for ; Wed, 24 Jul 2024 08:04:21 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=fail smtp.mailfrom=sughosh.ganu@linaro.org Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A4B6F106F; Tue, 23 Jul 2024 23:04:46 -0700 (PDT) Received: from a079122.blr.arm.com (a079122.arm.com [10.162.17.48]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 90A653F766; Tue, 23 Jul 2024 23:04:16 -0700 (PDT) From: Sughosh Ganu To: u-boot@lists.denx.de Cc: Ilias Apalodimas , Heinrich Schuchardt , Simon Glass , Marek Vasut , Mark Kettenis , Michal Simek , Patrick DELAUNAY , Patrice CHOTARD , Huan Wang , Angelo Dureghello , Daniel Schwierzeck , Thomas Chou , Rick Chen , Max Filippov , Sughosh Ganu Subject: [PATCH 19/40] lmb: reserve common areas during board init Date: Wed, 24 Jul 2024 11:32:03 +0530 Message-Id: <20240724060224.3071065-20-sughosh.ganu@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240724060224.3071065-1-sughosh.ganu@linaro.org> References: <20240724060224.3071065-1-sughosh.ganu@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The LMB module provides API's for allocating and reserving chunks of memory which is then typically used for things like loading images for booting. Reserve the portion of memory that is occupied by the U-Boot image itself, and other parts of memory that might have been marked as reserved in the board's DTB. When executing in SPL, reserve the sections that get relocated to the ram memory, the stack and the global data structure and also the bss. Mark these regions of memory with the LMB_NOOVERWRITE flag to indicate that these regions cannot be re-requested or overwritten. Signed-off-by: Sughosh Ganu Reviewed-by: Simon Glass --- Changes since rfc: * Add a function for reserving common areas in SPL, lmb_reserve_common_spl() lib/lmb.c | 36 ++++++++++++++++++++++++++++++++++-- 1 file changed, 34 insertions(+), 2 deletions(-) diff --git a/lib/lmb.c b/lib/lmb.c index f1142033ef..ce1b0204c9 100644 --- a/lib/lmb.c +++ b/lib/lmb.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include @@ -173,10 +174,11 @@ void arch_lmb_reserve_generic(ulong sp, ulong end, ulong align) if (bank_end > end) bank_end = end - 1; - lmb_reserve(sp, bank_end - sp + 1); + lmb_reserve_flags(sp, bank_end - sp + 1, LMB_NOOVERWRITE); if (gd->flags & GD_FLG_SKIP_RELOC) - lmb_reserve((phys_addr_t)(uintptr_t)_start, gd->mon_len); + lmb_reserve_flags((phys_addr_t)(uintptr_t)_start, + gd->mon_len, LMB_NOOVERWRITE); break; } @@ -226,6 +228,30 @@ static void lmb_reserve_common(void *fdt_blob) efi_lmb_reserve(); } +static __maybe_unused void lmb_reserve_common_spl(void) +{ + phys_addr_t rsv_start; + phys_size_t rsv_size; + + /* + * Assume a SPL stack of 16KB. This must be + * more than enough for the SPL stage. + */ + if (IS_ENABLED(CONFIG_SPL_STACK_R_ADDR)) { + rsv_start = gd->start_addr_sp - 16384; + rsv_size = 16384; + lmb_reserve_flags(rsv_start, rsv_size, LMB_NOOVERWRITE); + } + + if (IS_ENABLED(CONFIG_SPL_SEPARATE_BSS)) { + /* Reserve the bss region */ + rsv_start = (phys_addr_t)(uintptr_t)__bss_start; + rsv_size = (phys_addr_t)(uintptr_t)__bss_end - + (phys_addr_t)(uintptr_t)__bss_start; + lmb_reserve_flags(rsv_start, rsv_size, LMB_NOOVERWRITE); + } +} + /** * lmb_add_memory() - Add memory range for LMB allocations * @@ -757,5 +783,11 @@ int lmb_mem_regions_init(void) lmb_add_memory(); + /* Reserve the U-Boot image region once U-Boot has relocated */ + if (spl_phase() == PHASE_SPL) + lmb_reserve_common_spl(); + else if (spl_phase() == PHASE_BOARD_R) + lmb_reserve_common((void *)gd->fdt_blob); + return 0; }