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Mon, 22 Jul 2024 10:58:02 -0700 (PDT) Received: from localhost ([136.62.192.75]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-2610c771c34sm1757089fac.22.2024.07.22.10.58.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Jul 2024 10:58:02 -0700 (PDT) From: Sam Protsenko To: Minkyu Kang , Minkyu Kang Cc: Tom Rini , Peng Fan , Jaehoon Chung , Simon Glass , Quentin Schulz , Philipp Tomsich , Kever Yang , Eugeniy Paltsev , Peter Robinson , Jonas Karlman , Yang Xiwen , Ferass El Hafidi , Sean Anderson , u-boot@lists.denx.de, uboot-snps-arc@synopsys.com Subject: [PATCH v3 29/38] mmc: exynos_dw_mmc: Read and use DDR timing when available Date: Mon, 22 Jul 2024 12:57:31 -0500 Message-Id: <20240722175740.6985-30-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240722175740.6985-1-semen.protsenko@linaro.org> References: <20240722175740.6985-1-semen.protsenko@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean DDR timing values should be defined in "samsung,dw-mshc-ddr-timing" dts property, and used when DDR MMC mode is selected. Read that value from dts and use it. If it's not available, use SDR timing values instead. This change is following upstream Linux kernel implementation. Signed-off-by: Sam Protsenko --- Changes in v3: - (none) Changes in v2: - (none) drivers/mmc/exynos_dw_mmc.c | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c index b9d655c0d5c8..32f3ea168b6c 100644 --- a/drivers/mmc/exynos_dw_mmc.c +++ b/drivers/mmc/exynos_dw_mmc.c @@ -52,6 +52,7 @@ struct dwmci_exynos_priv_data { #endif struct clk clk; u32 sdr_timing; + u32 ddr_timing; const struct exynos_dwmmc_variant *chip; }; @@ -127,8 +128,14 @@ static int exynos_dwmmc_set_sclk(struct dwmci_host *host, unsigned long rate) static int exynos_dwmci_clksel(struct dwmci_host *host) { struct dwmci_exynos_priv_data *priv = exynos_dwmmc_get_priv(host); + u32 timing; - dwmci_writel(host, priv->chip->clksel, priv->sdr_timing); + if (host->mmc->selected_mode == MMC_DDR_52) + timing = priv->ddr_timing; + else + timing = priv->sdr_timing; + + dwmci_writel(host, priv->chip->clksel, timing); return 0; } @@ -305,6 +312,17 @@ static int exynos_dwmmc_of_to_plat(struct udevice *dev) priv->sdr_timing = DWMMC_MMC2_SDR_TIMING_VAL; } + err = dev_read_u32_array(dev, "samsung,dw-mshc-ddr-timing", timing, 2); + if (err) { + debug("DWMMC%d: Can't get ddr-timings, using sdr-timings\n", + host->dev_index); + priv->ddr_timing = priv->sdr_timing; + } else { + priv->ddr_timing = DWMCI_SET_SAMPLE_CLK(timing[0]) | + DWMCI_SET_DRV_CLK(timing[1]) | + DWMCI_SET_DIV_RATIO(div); + } + host->fifo_depth = dev_read_u32_default(dev, "fifo-depth", 0); host->bus_hz = dev_read_u32_default(dev, "clock-frequency", 0);