@@ -218,8 +218,6 @@ static unsigned int dwmci_get_timeout(struct mmc *mmc, const unsigned int size)
static int dwmci_data_transfer_fifo(struct dwmci_host *host,
struct mmc_data *data, u32 mask)
{
- const u32 fifo_depth = (((host->fifoth_val & RX_WMARK_MASK) >>
- RX_WMARK_SHIFT) + 1) * 2;
const u32 int_rx = mask & (DWMCI_INTMSK_RXDR | DWMCI_INTMSK_DTO);
const u32 int_tx = mask & DWMCI_INTMSK_TXDR;
int ret = 0;
@@ -254,8 +252,8 @@ static int dwmci_data_transfer_fifo(struct dwmci_host *host,
if (ret < 0)
break;
- len = fifo_depth - ((len >> DWMCI_FIFO_SHIFT) &
- DWMCI_FIFO_MASK);
+ len = host->fifo_depth - ((len >> DWMCI_FIFO_SHIFT) &
+ DWMCI_FIFO_MASK);
len = min(size, len);
for (i = 0; i < len; i++)
dwmci_writel(host, DWMCI_DATA, *buf++);
@@ -656,16 +654,23 @@ static int dwmci_set_ios(struct mmc *mmc)
static void dwmci_init_fifo(struct dwmci_host *host)
{
- if (!host->fifoth_val) {
+ u32 fifo_thr, fifoth_val;
+
+ if (!host->fifo_depth) {
u32 fifo_size;
+ /*
+ * Automatically detect FIFO depth from FIFOTH register.
+ * Power-on value of RX_WMark is FIFO_DEPTH-1.
+ */
fifo_size = dwmci_readl(host, DWMCI_FIFOTH);
fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1;
- host->fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size / 2 - 1) |
- TX_WMARK(fifo_size / 2);
+ host->fifo_depth = fifo_size;
}
- dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val);
+ fifo_thr = host->fifo_depth / 2;
+ fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_thr - 1) | TX_WMARK(fifo_thr);
+ dwmci_writel(host, DWMCI_FIFOTH, fifoth_val);
}
static void dwmci_init_dma(struct dwmci_host *host)
@@ -150,8 +150,8 @@ static int do_dwmci_init(struct dwmci_host *host)
return exynos_dwmci_core_init(host);
}
-static int exynos_dwmci_get_config(const void *blob, int node,
- struct dwmci_host *host,
+static int exynos_dwmci_get_config(struct udevice *dev, const void *blob,
+ int node, struct dwmci_host *host,
struct dwmci_exynos_priv_data *priv)
{
int err = 0;
@@ -200,7 +200,7 @@ static int exynos_dwmci_get_config(const void *blob, int node,
priv->sdr_timing = DWMMC_MMC2_SDR_TIMING_VAL;
}
- host->fifoth_val = fdtdec_get_int(blob, node, "fifoth_val", 0);
+ host->fifo_depth = dev_read_u32_default(dev, "fifo-depth", 0);
host->bus_hz = fdtdec_get_int(blob, node, "bus_hz", 0);
host->div = fdtdec_get_int(blob, node, "div", 0);
@@ -216,8 +216,8 @@ static int exynos_dwmmc_probe(struct udevice *dev)
struct dwmci_host *host = &priv->host;
int err;
- err = exynos_dwmci_get_config(gd->fdt_blob, dev_of_offset(dev), host,
- priv);
+ err = exynos_dwmci_get_config(dev, gd->fdt_blob, dev_of_offset(dev),
+ host, priv);
if (err)
return err;
err = do_dwmci_init(host);
@@ -28,7 +28,6 @@ struct ftsdc010_chip {
int dev_index;
int dev_id;
int buswidth;
- u32 fifoth_val;
struct mmc *mmc;
void *priv;
bool fifo_mode;
@@ -36,7 +36,7 @@ struct hi6220_dwmmc_priv_data {
struct hisi_mmc_data {
unsigned int clock;
bool use_fifo;
- u32 fifoth_val;
+ u32 fifo_depth;
};
static int hi6220_dwmmc_of_to_plat(struct udevice *dev)
@@ -125,7 +125,7 @@ static int hi6220_dwmmc_probe(struct udevice *dev)
host->mmc = &plat->mmc;
host->fifo_mode = mmc_data->use_fifo;
- host->fifoth_val = mmc_data->fifoth_val;
+ host->fifo_depth = mmc_data->fifo_depth;
host->mmc->priv = &priv->host;
upriv->mmc = host->mmc;
host->mmc->dev = dev;
@@ -158,8 +158,7 @@ static const struct hisi_mmc_data hi6220_mmc_data = {
static const struct hisi_mmc_data hi3798mv2x_mmc_data = {
.clock = 50000000,
.use_fifo = false,
- // FIFO depth is 256
- .fifoth_val = MSIZE(4) | RX_WMARK(0x7f) | TX_WMARK(0x80),
+ .fifo_depth = 256,
};
static const struct udevice_id hi6220_dwmmc_ids[] = {
@@ -186,10 +186,7 @@ static int nexell_dwmmc_probe(struct udevice *dev)
struct dwmci_host *host = &priv->host;
struct udevice *pwr_dev __maybe_unused;
- host->fifoth_val = MSIZE(0x2) |
- RX_WMARK(priv->fifo_size / 2 - 1) |
- TX_WMARK(priv->fifo_size / 2);
-
+ host->fifo_depth = priv->fifo_size;
host->fifo_mode = priv->fifo_mode;
dwmci_setup_cfg(&plat->cfg, host, priv->max_freq, priv->min_freq);
@@ -138,10 +138,7 @@ static int rockchip_dwmmc_probe(struct udevice *dev)
if (ret < 0)
return ret;
#endif
- host->fifoth_val = MSIZE(0x2) |
- RX_WMARK(priv->fifo_depth / 2 - 1) |
- TX_WMARK(priv->fifo_depth / 2);
-
+ host->fifo_depth = priv->fifo_depth;
host->fifo_mode = priv->fifo_mode;
#if CONFIG_IS_ENABLED(MMC_PWRSEQ)
@@ -81,7 +81,7 @@ static int snps_dwmmc_of_to_plat(struct udevice *dev)
host->ioaddr = dev_read_addr_ptr(dev);
/*
- * If fifo-depth is unset don't set fifoth_val - we will try to
+ * If fifo-depth is unset don't set fifo_depth - we will try to
* auto detect it.
*/
ret = dev_read_u32(dev, "fifo-depth", &fifo_depth);
@@ -89,9 +89,7 @@ static int snps_dwmmc_of_to_plat(struct udevice *dev)
if (fifo_depth < FIFO_MIN || fifo_depth > FIFO_MAX)
return -EINVAL;
- host->fifoth_val = MSIZE(0x2) |
- RX_WMARK(fifo_depth / 2 - 1) |
- TX_WMARK(fifo_depth / 2);
+ host->fifo_depth = fifo_depth;
}
host->buswidth = dev_read_u32_default(dev, "bus-width", 4);
@@ -134,8 +134,8 @@ static int socfpga_dwmmc_of_to_plat(struct udevice *dev)
* We only have one dwmmc block on gen5 SoCFPGA.
*/
host->dev_index = 0;
- host->fifoth_val = MSIZE(0x2) |
- RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2);
+
+ host->fifo_depth = fifo_depth;
priv->drvsel = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
"drvsel", 3);
priv->smplsel = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
@@ -187,7 +187,7 @@ struct dwmci_idmac_regs {
* @dev_index: Arbitrary device index for use by controller
* @dev_id: Arbitrary device ID for use by controller
* @buswidth: Bus width in bits (8 or 4)
- * @fifoth_val: Value for FIFOTH register (or 0 to leave unset)
+ * @fifo_depth: Depth of FIFO, bytes (or 0 for automatic detection)
* @mmc: Pointer to generic MMC structure for this device
* @priv: Private pointer for use by controller
* @dma_64bit_address: Whether DMA supports 64-bit address mode or not
@@ -204,7 +204,7 @@ struct dwmci_host {
int dev_index;
int dev_id;
int buswidth;
- u32 fifoth_val;
+ u32 fifo_depth;
struct mmc *mmc;
void *priv;
Replace fifoth_val property with its fifo-depth counterpart in all DW MMC drivers. fifo-depth is a common property used in upstream Linux kernel. The FIFOTH register value will be calculated using fifo-depth value in DW MMC core (dw_mmc.c). This change reduces code duplication in platform drivers, and pulls common FIFOTH register value calculation into core dw_mmc driver where it belongs. No functional change. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> --- Changes in v3: - (none) Changes in v2: - (none) drivers/mmc/dw_mmc.c | 21 +++++++++++++-------- drivers/mmc/exynos_dw_mmc.c | 10 +++++----- drivers/mmc/ftsdc010_mci.h | 1 - drivers/mmc/hi6220_dw_mmc.c | 7 +++---- drivers/mmc/nexell_dw_mmc.c | 5 +---- drivers/mmc/rockchip_dw_mmc.c | 5 +---- drivers/mmc/snps_dw_mmc.c | 6 ++---- drivers/mmc/socfpga_dw_mmc.c | 4 ++-- include/dwmmc.h | 4 ++-- 9 files changed, 29 insertions(+), 34 deletions(-)