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[92.17.96.232]) by smtp.gmail.com with ESMTPSA id y13-20020a5d4acd000000b00341e5f487casm2292237wrs.46.2024.03.28.10.59.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Mar 2024 10:59:46 -0700 (PDT) From: Caleb Connolly Date: Thu, 28 Mar 2024 17:59:12 +0000 Subject: [PATCH v5 06/16] clk/qcom: sdm845: add gdscs MIME-Version: 1.0 Message-Id: <20240328-b4-qcom-livetree-v5-6-4e98228b3d03@linaro.org> References: <20240328-b4-qcom-livetree-v5-0-4e98228b3d03@linaro.org> In-Reply-To: <20240328-b4-qcom-livetree-v5-0-4e98228b3d03@linaro.org> To: Tom Rini , Caleb Connolly , Neil Armstrong , Sumit Garg , Lukasz Majewski , Sean Anderson Cc: u-boot@lists.denx.de X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=1714; i=caleb.connolly@linaro.org; h=from:subject:message-id; bh=J2wyNARYq0khhF05IOZjfXaKY3NwgELyfaNZ+Dn9LDc=; b=owGbwMvMwCFYaeA6f6eBkTjjabUkhjTWDZypKrqLKmf87QpfNCPp2mVmn2/tyd1Jn9ztfC9HX 7229W1RRykLgyAHg6yYIov4iWWWTWsv22tsX3ABZg4rE8gQBi5OAZhI9G9Ghs7wg9ELe/d9rI89 KF7weP33cqWG5aH/8t1UohMvf33+KJvhn8LklBMNnVUmJmtZRJ3cLRxYk53q9FcInfHbnOxhNl+ oHQA= X-Developer-Key: i=caleb.connolly@linaro.org; a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Define the GDSC power domains for SDM845. Reviewed-by: Neil Armstrong Reviewed-by: Sumit Garg Signed-off-by: Caleb Connolly --- drivers/clk/qcom/clock-sdm845.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/clk/qcom/clock-sdm845.c b/drivers/clk/qcom/clock-sdm845.c index ccb0cf245d33..b7154360894a 100644 --- a/drivers/clk/qcom/clock-sdm845.c +++ b/drivers/clk/qcom/clock-sdm845.c @@ -145,13 +145,31 @@ static const struct qcom_reset_map sdm845_gcc_resets[] = { [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 }, [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, }; +static const struct qcom_power_map sdm845_gdscs[] = { + [PCIE_0_GDSC] = { 0x6b004 }, + [PCIE_1_GDSC] = { 0x8d004 }, + [UFS_CARD_GDSC] = { 0x75004 }, + [UFS_PHY_GDSC] = { 0x77004 }, + [USB30_PRIM_GDSC] = { 0xf004 }, + [USB30_SEC_GDSC] = { 0x10004 }, + [HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC] = { 0x7d030 }, + [HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC] = { 0x7d03c }, + [HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC] = { 0x7d034 }, + [HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC] = { 0x7d038 }, + [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = { 0x7d040 }, + [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = { 0x7d048 }, + [HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] = { 0x7d044 }, +}; + static struct msm_clk_data sdm845_clk_data = { .resets = sdm845_gcc_resets, .num_resets = ARRAY_SIZE(sdm845_gcc_resets), .clks = sdm845_clks, .num_clks = ARRAY_SIZE(sdm845_clks), + .power_domains = sdm845_gdscs, + .num_power_domains = ARRAY_SIZE(sdm845_gdscs), .enable = sdm845_clk_enable, .set_rate = sdm845_clk_set_rate, };