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([223.178.211.159]) by smtp.gmail.com with ESMTPSA id j9-20020a170902da8900b001dddb014624sm11751668plx.54.2024.03.21.07.55.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Mar 2024 07:55:53 -0700 (PDT) From: Sumit Garg To: u-boot@lists.denx.de Cc: trini@konsulko.com, tharvey@gateworks.com, marcel.ziswiler@toradex.com, francesco@dolcini.it, lukma@denx.de, seanga2@gmail.com, jh80.chung@samsung.com, sjg@chromium.org, festevam@denx.de, andrejs.cainikovs@toradex.com, peng.fan@nxp.com, aford173@gmail.com, marex@denx.de, ilias.apalodimas@linaro.org, sahaj.sarup@linaro.org, fathi.boudra@linaro.org, remi.duraffort@linaro.org, daniel.thompson@linaro.org, pbrobinson@gmail.com, Sumit Garg Subject: [PATCH v4 05/11] imx8mp: power-domain: Expose high performance PLL clock Date: Thu, 21 Mar 2024 20:25:01 +0530 Message-Id: <20240321145507.619448-6-sumit.garg@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240321145507.619448-1-sumit.garg@linaro.org> References: <20240321145507.619448-1-sumit.garg@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Expose the high performance PLL as clock framework clock, so the PCIe PHY can use it when there is no external refclock provided. Inspired from counterpart Linux kernel v6.8-rc3 driver: drivers/pmdomain/imx/imx8mp-blk-ctrl.c. Use last Linux kernel driver reference commit 7476ddfd36ac ("pmdomain: imx8mp-blk-ctrl: Convert to platform remove callback returning void"). Tested-by: Tim Harvey #imx8mp-venice* Tested-by: Adam Ford #imx8mp-beacon-kit Reviewed-by: Marek Vasut Signed-off-by: Sumit Garg --- drivers/power/domain/imx8mp-hsiomix.c | 77 +++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) diff --git a/drivers/power/domain/imx8mp-hsiomix.c b/drivers/power/domain/imx8mp-hsiomix.c index d3b0c1146ce..6188a04c45e 100644 --- a/drivers/power/domain/imx8mp-hsiomix.c +++ b/drivers/power/domain/imx8mp-hsiomix.c @@ -6,9 +6,15 @@ #include #include #include +#include #include #include #include +#include +#include +#include +#include +#include #include #include @@ -18,6 +24,15 @@ #define USB_CLOCK_MODULE_EN BIT(1) #define PCIE_PHY_APB_RST BIT(4) #define PCIE_PHY_INIT_RST BIT(5) +#define GPR_REG1 0x4 +#define PLL_LOCK BIT(13) +#define GPR_REG2 0x8 +#define P_PLL_MASK GENMASK(5, 0) +#define M_PLL_MASK GENMASK(15, 6) +#define S_PLL_MASK GENMASK(18, 16) +#define GPR_REG3 0xc +#define PLL_CKE BIT(17) +#define PLL_RST BIT(31) struct imx8mp_hsiomix_priv { void __iomem *base; @@ -123,6 +138,67 @@ static int imx8mp_hsiomix_of_xlate(struct power_domain *power_domain, return 0; } +static int hsio_pll_clk_enable(struct clk *clk) +{ + void *base = (void *)dev_get_driver_data(clk->dev); + u32 val; + int ret; + + /* Setup HSIO PLL as 100 MHz output clock */ + clrsetbits_le32(base + GPR_REG2, + P_PLL_MASK | M_PLL_MASK | S_PLL_MASK, + FIELD_PREP(P_PLL_MASK, 12) | + FIELD_PREP(M_PLL_MASK, 800) | + FIELD_PREP(S_PLL_MASK, 4)); + + /* de-assert PLL reset */ + setbits_le32(base + GPR_REG3, PLL_RST); + + /* enable PLL */ + setbits_le32(base + GPR_REG3, PLL_CKE); + + /* Check if PLL is locked */ + ret = readl_poll_sleep_timeout(base + GPR_REG1, val, + val & PLL_LOCK, 10, 100000); + if (ret) + dev_err(clk->dev, "failed to lock HSIO PLL\n"); + + return ret; +} + +static int hsio_pll_clk_disable(struct clk *clk) +{ + void *base = (void *)dev_get_driver_data(clk->dev); + + clrbits_le32(base + GPR_REG3, PLL_CKE | PLL_RST); + + return 0; +} + +static const struct clk_ops hsio_pll_clk_ops = { + .enable = hsio_pll_clk_enable, + .disable = hsio_pll_clk_disable, +}; + +U_BOOT_DRIVER(hsio_pll) = { + .name = "hsio-pll", + .id = UCLASS_CLK, + .ops = &hsio_pll_clk_ops, +}; + +int imx8mp_hsiomix_bind(struct udevice *dev) +{ + struct driver *drv; + + drv = lists_driver_lookup_name("hsio-pll"); + if (!drv) + return -ENOENT; + + return device_bind_with_driver_data(dev, drv, "hsio-pll", + (ulong)dev_read_addr_ptr(dev), + dev_ofnode(dev), NULL); +} + static int imx8mp_hsiomix_probe(struct udevice *dev) { struct imx8mp_hsiomix_priv *priv = dev_get_priv(dev); @@ -193,6 +269,7 @@ U_BOOT_DRIVER(imx8mp_hsiomix) = { .id = UCLASS_POWER_DOMAIN, .of_match = imx8mp_hsiomix_ids, .probe = imx8mp_hsiomix_probe, + .bind = imx8mp_hsiomix_bind, .priv_auto = sizeof(struct imx8mp_hsiomix_priv), .ops = &imx8mp_hsiomix_ops, };