diff --git a/arch/arm/dts/tegra186.dtsi b/arch/arm/dts/tegra186.dtsi
index edcb7aacb8ee..58dadc944888 100644
--- a/arch/arm/dts/tegra186.dtsi
+++ b/arch/arm/dts/tegra186.dtsi
@@ -313,9 +313,9 @@
 	};
 
 	bpmp: bpmp {
 		compatible = "nvidia,tegra186-bpmp";
-		mboxes = <&hsp HSP_MBOX_TYPE_DB HSP_DB_MASTER_BPMP>;
+		mboxes = <&hsp TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_BPMP>;
 		/*
 		 * In theory, these references, and the configuration in the
 		 * node these reference point at, are board-specific, since
 		 * they depend on the BCT's memory carve-out setup, the
diff --git a/drivers/mailbox/tegra-hsp.c b/drivers/mailbox/tegra-hsp.c
index 08c51c40f141..e5a3d8243780 100644
--- a/drivers/mailbox/tegra-hsp.c
+++ b/drivers/mailbox/tegra-hsp.c
@@ -62,9 +62,9 @@ static void tegra_hsp_writel(struct tegra_hsp *thsp, uint32_t val,
 
 static int tegra_hsp_db_id(ulong chan_id)
 {
 	switch (chan_id) {
-	case (HSP_MBOX_TYPE_DB << 16) | HSP_DB_MASTER_BPMP:
+	case (TEGRA_HSP_MBOX_TYPE_DB << 16) | TEGRA_HSP_DB_MASTER_BPMP:
 		return TEGRA_HSP_DB_ID_BPMP;
 	default:
 		debug("Invalid channel ID\n");
 		return -EINVAL;
diff --git a/include/dt-bindings/gpio/tegra-gpio.h b/include/dt-bindings/gpio/tegra-gpio.h
deleted file mode 100644
index a1c09e88e80b..000000000000
--- a/include/dt-bindings/gpio/tegra-gpio.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This header provides constants for binding nvidia,tegra*-gpio.
- *
- * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below
- * provide names for this.
- *
- * The second cell contains standard flag values specified in gpio.h.
- */
-
-#ifndef _DT_BINDINGS_GPIO_TEGRA_GPIO_H
-#define _DT_BINDINGS_GPIO_TEGRA_GPIO_H
-
-#include <dt-bindings/gpio/gpio.h>
-
-#define TEGRA_GPIO_PORT_A 0
-#define TEGRA_GPIO_PORT_B 1
-#define TEGRA_GPIO_PORT_C 2
-#define TEGRA_GPIO_PORT_D 3
-#define TEGRA_GPIO_PORT_E 4
-#define TEGRA_GPIO_PORT_F 5
-#define TEGRA_GPIO_PORT_G 6
-#define TEGRA_GPIO_PORT_H 7
-#define TEGRA_GPIO_PORT_I 8
-#define TEGRA_GPIO_PORT_J 9
-#define TEGRA_GPIO_PORT_K 10
-#define TEGRA_GPIO_PORT_L 11
-#define TEGRA_GPIO_PORT_M 12
-#define TEGRA_GPIO_PORT_N 13
-#define TEGRA_GPIO_PORT_O 14
-#define TEGRA_GPIO_PORT_P 15
-#define TEGRA_GPIO_PORT_Q 16
-#define TEGRA_GPIO_PORT_R 17
-#define TEGRA_GPIO_PORT_S 18
-#define TEGRA_GPIO_PORT_T 19
-#define TEGRA_GPIO_PORT_U 20
-#define TEGRA_GPIO_PORT_V 21
-#define TEGRA_GPIO_PORT_W 22
-#define TEGRA_GPIO_PORT_X 23
-#define TEGRA_GPIO_PORT_Y 24
-#define TEGRA_GPIO_PORT_Z 25
-#define TEGRA_GPIO_PORT_AA 26
-#define TEGRA_GPIO_PORT_BB 27
-#define TEGRA_GPIO_PORT_CC 28
-#define TEGRA_GPIO_PORT_DD 29
-#define TEGRA_GPIO_PORT_EE 30
-#define TEGRA_GPIO_PORT_FF 31
-
-#define TEGRA_GPIO(port, offset) \
-	((TEGRA_GPIO_PORT_##port * 8) + offset)
-
-#endif
diff --git a/include/dt-bindings/mailbox/tegra186-hsp.h b/include/dt-bindings/mailbox/tegra186-hsp.h
deleted file mode 100644
index b4864325d74b..000000000000
--- a/include/dt-bindings/mailbox/tegra186-hsp.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * This header provides constants for binding nvidia,tegra186-hsp.
- *
- * The number with HSP_DB_MASTER prefix indicates the bit that is
- * associated with a master ID in the doorbell registers.
- */
-
-#ifndef _DT_BINDINGS_MAILBOX_TEGRA186_HSP_H
-#define _DT_BINDINGS_MAILBOX_TEGRA186_HSP_H
-
-#define HSP_MBOX_TYPE_DB 0x0
-#define HSP_MBOX_TYPE_SM 0x1
-#define HSP_MBOX_TYPE_SS 0x2
-#define HSP_MBOX_TYPE_AS 0x3
-
-#define HSP_DB_MASTER_CCPLEX 17
-#define HSP_DB_MASTER_BPMP 19
-
-#endif
diff --git a/include/dt-bindings/memory/tegra114-mc.h b/include/dt-bindings/memory/tegra114-mc.h
deleted file mode 100644
index 8f48985a3139..000000000000
--- a/include/dt-bindings/memory/tegra114-mc.h
+++ /dev/null
@@ -1,25 +0,0 @@
-#ifndef DT_BINDINGS_MEMORY_TEGRA114_MC_H
-#define DT_BINDINGS_MEMORY_TEGRA114_MC_H
-
-#define TEGRA_SWGROUP_PTC	0
-#define TEGRA_SWGROUP_DC	1
-#define TEGRA_SWGROUP_DCB	2
-#define TEGRA_SWGROUP_EPP	3
-#define TEGRA_SWGROUP_G2	4
-#define TEGRA_SWGROUP_AVPC	5
-#define TEGRA_SWGROUP_NV	6
-#define TEGRA_SWGROUP_HDA	7
-#define TEGRA_SWGROUP_HC	8
-#define TEGRA_SWGROUP_MSENC	9
-#define TEGRA_SWGROUP_PPCS	10
-#define TEGRA_SWGROUP_VDE	11
-#define TEGRA_SWGROUP_MPCORELP	12
-#define TEGRA_SWGROUP_MPCORE	13
-#define TEGRA_SWGROUP_VI	14
-#define TEGRA_SWGROUP_ISP	15
-#define TEGRA_SWGROUP_XUSB_HOST	16
-#define TEGRA_SWGROUP_XUSB_DEV	17
-#define TEGRA_SWGROUP_EMUCIF	18
-#define TEGRA_SWGROUP_TSEC	19
-
-#endif
diff --git a/include/dt-bindings/memory/tegra124-mc.h b/include/dt-bindings/memory/tegra124-mc.h
deleted file mode 100644
index 7d8ee798f34e..000000000000
--- a/include/dt-bindings/memory/tegra124-mc.h
+++ /dev/null
@@ -1,31 +0,0 @@
-#ifndef DT_BINDINGS_MEMORY_TEGRA124_MC_H
-#define DT_BINDINGS_MEMORY_TEGRA124_MC_H
-
-#define TEGRA_SWGROUP_PTC	0
-#define TEGRA_SWGROUP_DC	1
-#define TEGRA_SWGROUP_DCB	2
-#define TEGRA_SWGROUP_AFI	3
-#define TEGRA_SWGROUP_AVPC	4
-#define TEGRA_SWGROUP_HDA	5
-#define TEGRA_SWGROUP_HC	6
-#define TEGRA_SWGROUP_MSENC	7
-#define TEGRA_SWGROUP_PPCS	8
-#define TEGRA_SWGROUP_SATA	9
-#define TEGRA_SWGROUP_VDE	10
-#define TEGRA_SWGROUP_MPCORELP	11
-#define TEGRA_SWGROUP_MPCORE	12
-#define TEGRA_SWGROUP_ISP2	13
-#define TEGRA_SWGROUP_XUSB_HOST	14
-#define TEGRA_SWGROUP_XUSB_DEV	15
-#define TEGRA_SWGROUP_ISP2B	16
-#define TEGRA_SWGROUP_TSEC	17
-#define TEGRA_SWGROUP_A9AVP	18
-#define TEGRA_SWGROUP_GPU	19
-#define TEGRA_SWGROUP_SDMMC1A	20
-#define TEGRA_SWGROUP_SDMMC2A	21
-#define TEGRA_SWGROUP_SDMMC3A	22
-#define TEGRA_SWGROUP_SDMMC4A	23
-#define TEGRA_SWGROUP_VIC	24
-#define TEGRA_SWGROUP_VI	25
-
-#endif
diff --git a/include/dt-bindings/memory/tegra210-mc.h b/include/dt-bindings/memory/tegra210-mc.h
deleted file mode 100644
index d1731bc14dbc..000000000000
--- a/include/dt-bindings/memory/tegra210-mc.h
+++ /dev/null
@@ -1,36 +0,0 @@
-#ifndef DT_BINDINGS_MEMORY_TEGRA210_MC_H
-#define DT_BINDINGS_MEMORY_TEGRA210_MC_H
-
-#define TEGRA_SWGROUP_PTC	0
-#define TEGRA_SWGROUP_DC	1
-#define TEGRA_SWGROUP_DCB	2
-#define TEGRA_SWGROUP_AFI	3
-#define TEGRA_SWGROUP_AVPC	4
-#define TEGRA_SWGROUP_HDA	5
-#define TEGRA_SWGROUP_HC	6
-#define TEGRA_SWGROUP_NVENC	7
-#define TEGRA_SWGROUP_PPCS	8
-#define TEGRA_SWGROUP_SATA	9
-#define TEGRA_SWGROUP_MPCORE	10
-#define TEGRA_SWGROUP_ISP2	11
-#define TEGRA_SWGROUP_XUSB_HOST	12
-#define TEGRA_SWGROUP_XUSB_DEV	13
-#define TEGRA_SWGROUP_ISP2B	14
-#define TEGRA_SWGROUP_TSEC	15
-#define TEGRA_SWGROUP_A9AVP	16
-#define TEGRA_SWGROUP_GPU	17
-#define TEGRA_SWGROUP_SDMMC1A	18
-#define TEGRA_SWGROUP_SDMMC2A	19
-#define TEGRA_SWGROUP_SDMMC3A	20
-#define TEGRA_SWGROUP_SDMMC4A	21
-#define TEGRA_SWGROUP_VIC	22
-#define TEGRA_SWGROUP_VI	23
-#define TEGRA_SWGROUP_NVDEC	24
-#define TEGRA_SWGROUP_APE	25
-#define TEGRA_SWGROUP_NVJPG	26
-#define TEGRA_SWGROUP_SE	27
-#define TEGRA_SWGROUP_AXIAP	28
-#define TEGRA_SWGROUP_ETR	29
-#define TEGRA_SWGROUP_TSECB	30
-
-#endif
diff --git a/include/dt-bindings/memory/tegra30-mc.h b/include/dt-bindings/memory/tegra30-mc.h
deleted file mode 100644
index 502beb03d777..000000000000
--- a/include/dt-bindings/memory/tegra30-mc.h
+++ /dev/null
@@ -1,24 +0,0 @@
-#ifndef DT_BINDINGS_MEMORY_TEGRA30_MC_H
-#define DT_BINDINGS_MEMORY_TEGRA30_MC_H
-
-#define TEGRA_SWGROUP_PTC	0
-#define TEGRA_SWGROUP_DC	1
-#define TEGRA_SWGROUP_DCB	2
-#define TEGRA_SWGROUP_EPP	3
-#define TEGRA_SWGROUP_G2	4
-#define TEGRA_SWGROUP_MPE	5
-#define TEGRA_SWGROUP_VI	6
-#define TEGRA_SWGROUP_AFI	7
-#define TEGRA_SWGROUP_AVPC	8
-#define TEGRA_SWGROUP_NV	9
-#define TEGRA_SWGROUP_NV2	10
-#define TEGRA_SWGROUP_HDA	11
-#define TEGRA_SWGROUP_HC	12
-#define TEGRA_SWGROUP_PPCS	13
-#define TEGRA_SWGROUP_SATA	14
-#define TEGRA_SWGROUP_VDE	15
-#define TEGRA_SWGROUP_MPCORELP	16
-#define TEGRA_SWGROUP_MPCORE	17
-#define TEGRA_SWGROUP_ISP	18
-
-#endif
diff --git a/include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h b/include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h
deleted file mode 100644
index 914d56da9324..000000000000
--- a/include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef _DT_BINDINGS_PINCTRL_TEGRA_XUSB_H
-#define _DT_BINDINGS_PINCTRL_TEGRA_XUSB_H 1
-
-#define TEGRA_XUSB_PADCTL_PCIE 0
-#define TEGRA_XUSB_PADCTL_SATA 1
-
-#endif /* _DT_BINDINGS_PINCTRL_TEGRA_XUSB_H */
diff --git a/include/dt-bindings/pinctrl/pinctrl-tegra.h b/include/dt-bindings/pinctrl/pinctrl-tegra.h
deleted file mode 100644
index c9b57408de68..000000000000
--- a/include/dt-bindings/pinctrl/pinctrl-tegra.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * This header provides constants for Tegra pinctrl bindings.
- *
- * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
- *
- * Author: Laxman Dewangan <ldewangan@nvidia.com>
- */
-
-#ifndef _DT_BINDINGS_PINCTRL_TEGRA_H
-#define _DT_BINDINGS_PINCTRL_TEGRA_H
-
-/*
- * Enable/disable for diffeent dt properties. This is applicable for
- * properties nvidia,enable-input, nvidia,tristate, nvidia,open-drain,
- * nvidia,lock, nvidia,rcv-sel, nvidia,high-speed-mode, nvidia,schmitt.
- */
-#define TEGRA_PIN_DISABLE				0
-#define TEGRA_PIN_ENABLE				1
-
-#define TEGRA_PIN_PULL_NONE				0
-#define TEGRA_PIN_PULL_DOWN				1
-#define TEGRA_PIN_PULL_UP				2
-
-/* Low power mode driver */
-#define TEGRA_PIN_LP_DRIVE_DIV_8			0
-#define TEGRA_PIN_LP_DRIVE_DIV_4			1
-#define TEGRA_PIN_LP_DRIVE_DIV_2			2
-#define TEGRA_PIN_LP_DRIVE_DIV_1			3
-
-/* Rising/Falling slew rate */
-#define TEGRA_PIN_SLEW_RATE_FASTEST			0
-#define TEGRA_PIN_SLEW_RATE_FAST			1
-#define TEGRA_PIN_SLEW_RATE_SLOW			2
-#define TEGRA_PIN_SLEW_RATE_SLOWEST			3
-
-#endif
diff --git a/include/dt-bindings/power/tegra186-powergate.h b/include/dt-bindings/power/tegra186-powergate.h
deleted file mode 100644
index 17e75498563c..000000000000
--- a/include/dt-bindings/power/tegra186-powergate.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2015-2016, NVIDIA CORPORATION.
- */
-
-#ifndef _DT_BINDINGS_POWER_TEGRA186_POWERGATE_H
-#define _DT_BINDINGS_POWER_TEGRA186_POWERGATE_H
-
-#define TEGRA186_POWER_DOMAIN_AUD	0
-#define TEGRA186_POWER_DOMAIN_DFD	1
-#define TEGRA186_POWER_DOMAIN_DISP	2
-#define TEGRA186_POWER_DOMAIN_DISPB	3
-#define TEGRA186_POWER_DOMAIN_DISPC	4
-#define TEGRA186_POWER_DOMAIN_ISPA	5
-#define TEGRA186_POWER_DOMAIN_NVDEC	6
-#define TEGRA186_POWER_DOMAIN_NVJPG	7
-#define TEGRA186_POWER_DOMAIN_MPE	8
-#define TEGRA186_POWER_DOMAIN_PCX	9
-#define TEGRA186_POWER_DOMAIN_SAX	10
-#define TEGRA186_POWER_DOMAIN_VE	11
-#define TEGRA186_POWER_DOMAIN_VIC	12
-#define TEGRA186_POWER_DOMAIN_XUSBA	13
-#define TEGRA186_POWER_DOMAIN_XUSBB	14
-#define TEGRA186_POWER_DOMAIN_XUSBC	15
-#define TEGRA186_POWER_DOMAIN_GPU	43
-#define TEGRA186_POWER_DOMAIN_MAX	44
-
-#endif
diff --git a/include/dt-bindings/reset/tegra124-car.h b/include/dt-bindings/reset/tegra124-car.h
deleted file mode 100644
index 070e4f6e7486..000000000000
--- a/include/dt-bindings/reset/tegra124-car.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * This header provides Tegra124-specific constants for binding
- * nvidia,tegra124-car.
- */
-
-#ifndef _DT_BINDINGS_RESET_TEGRA124_CAR_H
-#define _DT_BINDINGS_RESET_TEGRA124_CAR_H
-
-#define TEGRA124_RESET(x)		(6 * 32 + (x))
-#define TEGRA124_RST_DFLL_DVCO		TEGRA124_RESET(0)
-
-#endif	/* _DT_BINDINGS_RESET_TEGRA124_CAR_H */
diff --git a/include/dt-bindings/reset/tegra186-reset.h b/include/dt-bindings/reset/tegra186-reset.h
deleted file mode 100644
index 7efec9200532..000000000000
--- a/include/dt-bindings/reset/tegra186-reset.h
+++ /dev/null
@@ -1,205 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2015, NVIDIA CORPORATION.
- */
-
-#ifndef _ABI_MACH_T186_RESET_T186_H_
-#define _ABI_MACH_T186_RESET_T186_H_
-
-#define TEGRA186_RESET_ACTMON			0
-#define TEGRA186_RESET_AFI			1
-#define TEGRA186_RESET_CEC			2
-#define TEGRA186_RESET_CSITE			3
-#define TEGRA186_RESET_DP2			4
-#define TEGRA186_RESET_DPAUX			5
-#define TEGRA186_RESET_DSI			6
-#define TEGRA186_RESET_DSIB			7
-#define TEGRA186_RESET_DTV			8
-#define TEGRA186_RESET_DVFS			9
-#define TEGRA186_RESET_ENTROPY			10
-#define TEGRA186_RESET_EXTPERIPH1		11
-#define TEGRA186_RESET_EXTPERIPH2		12
-#define TEGRA186_RESET_EXTPERIPH3		13
-#define TEGRA186_RESET_GPU			14
-#define TEGRA186_RESET_HDA			15
-#define TEGRA186_RESET_HDA2CODEC_2X		16
-#define TEGRA186_RESET_HDA2HDMICODEC		17
-#define TEGRA186_RESET_HOST1X			18
-#define TEGRA186_RESET_I2C1			19
-#define TEGRA186_RESET_I2C2			20
-#define TEGRA186_RESET_I2C3			21
-#define TEGRA186_RESET_I2C4			22
-#define TEGRA186_RESET_I2C5			23
-#define TEGRA186_RESET_I2C6			24
-#define TEGRA186_RESET_ISP			25
-#define TEGRA186_RESET_KFUSE			26
-#define TEGRA186_RESET_LA			27
-#define TEGRA186_RESET_MIPI_CAL			28
-#define TEGRA186_RESET_PCIE			29
-#define TEGRA186_RESET_PCIEXCLK			30
-#define TEGRA186_RESET_SATA			31
-#define TEGRA186_RESET_SATACOLD			32
-#define TEGRA186_RESET_SDMMC1			33
-#define TEGRA186_RESET_SDMMC2			34
-#define TEGRA186_RESET_SDMMC3			35
-#define TEGRA186_RESET_SDMMC4			36
-#define TEGRA186_RESET_SE			37
-#define TEGRA186_RESET_SOC_THERM		38
-#define TEGRA186_RESET_SOR0			39
-#define TEGRA186_RESET_SPI1			40
-#define TEGRA186_RESET_SPI2			41
-#define TEGRA186_RESET_SPI3			42
-#define TEGRA186_RESET_SPI4			43
-#define TEGRA186_RESET_TMR			44
-#define TEGRA186_RESET_TRIG_SYS			45
-#define TEGRA186_RESET_TSEC			46
-#define TEGRA186_RESET_UARTA			47
-#define TEGRA186_RESET_UARTB			48
-#define TEGRA186_RESET_UARTC			49
-#define TEGRA186_RESET_UARTD			50
-#define TEGRA186_RESET_VI			51
-#define TEGRA186_RESET_VIC			52
-#define TEGRA186_RESET_XUSB_DEV			53
-#define TEGRA186_RESET_XUSB_HOST		54
-#define TEGRA186_RESET_XUSB_PADCTL		55
-#define TEGRA186_RESET_XUSB_SS			56
-#define TEGRA186_RESET_AON_APB			57
-#define TEGRA186_RESET_AXI_CBB			58
-#define TEGRA186_RESET_BPMP_APB			59
-#define TEGRA186_RESET_CAN1			60
-#define TEGRA186_RESET_CAN2			61
-#define TEGRA186_RESET_DMIC5			62
-#define TEGRA186_RESET_DSIC			63
-#define TEGRA186_RESET_DSID			64
-#define TEGRA186_RESET_EMC_EMC			65
-#define TEGRA186_RESET_EMC_MEM			66
-#define TEGRA186_RESET_EMCSB_EMC		67
-#define TEGRA186_RESET_EMCSB_MEM		68
-#define TEGRA186_RESET_EQOS			69
-#define TEGRA186_RESET_GPCDMA			70
-#define TEGRA186_RESET_GPIO_CTL0		71
-#define TEGRA186_RESET_GPIO_CTL1		72
-#define TEGRA186_RESET_GPIO_CTL2		73
-#define TEGRA186_RESET_GPIO_CTL3		74
-#define TEGRA186_RESET_GPIO_CTL4		75
-#define TEGRA186_RESET_GPIO_CTL5		76
-#define TEGRA186_RESET_I2C10			77
-#define TEGRA186_RESET_I2C12			78
-#define TEGRA186_RESET_I2C13			79
-#define TEGRA186_RESET_I2C14			80
-#define TEGRA186_RESET_I2C7			81
-#define TEGRA186_RESET_I2C8			82
-#define TEGRA186_RESET_I2C9			83
-#define TEGRA186_RESET_JTAG2AXI			84
-#define TEGRA186_RESET_MPHY_IOBIST		85
-#define TEGRA186_RESET_MPHY_L0_RX		86
-#define TEGRA186_RESET_MPHY_L0_TX		87
-#define TEGRA186_RESET_NVCSI			88
-#define TEGRA186_RESET_NVDISPLAY0_HEAD0		89
-#define TEGRA186_RESET_NVDISPLAY0_HEAD1		90
-#define TEGRA186_RESET_NVDISPLAY0_HEAD2		91
-#define TEGRA186_RESET_NVDISPLAY0_MISC		92
-#define TEGRA186_RESET_NVDISPLAY0_WGRP0		93
-#define TEGRA186_RESET_NVDISPLAY0_WGRP1		94
-#define TEGRA186_RESET_NVDISPLAY0_WGRP2		95
-#define TEGRA186_RESET_NVDISPLAY0_WGRP3		96
-#define TEGRA186_RESET_NVDISPLAY0_WGRP4		97
-#define TEGRA186_RESET_NVDISPLAY0_WGRP5		98
-#define TEGRA186_RESET_PWM1			99
-#define TEGRA186_RESET_PWM2			100
-#define TEGRA186_RESET_PWM3			101
-#define TEGRA186_RESET_PWM4			102
-#define TEGRA186_RESET_PWM5			103
-#define TEGRA186_RESET_PWM6			104
-#define TEGRA186_RESET_PWM7			105
-#define TEGRA186_RESET_PWM8			106
-#define TEGRA186_RESET_SCE_APB			107
-#define TEGRA186_RESET_SOR1			108
-#define TEGRA186_RESET_TACH			109
-#define TEGRA186_RESET_TSC			110
-#define TEGRA186_RESET_UARTF			111
-#define TEGRA186_RESET_UARTG			112
-#define TEGRA186_RESET_UFSHC			113
-#define TEGRA186_RESET_UFSHC_AXI_M		114
-#define TEGRA186_RESET_UPHY			115
-#define TEGRA186_RESET_ADSP			116
-#define TEGRA186_RESET_ADSPDBG			117
-#define TEGRA186_RESET_ADSPINTF			118
-#define TEGRA186_RESET_ADSPNEON			119
-#define TEGRA186_RESET_ADSPPERIPH		120
-#define TEGRA186_RESET_ADSPSCU			121
-#define TEGRA186_RESET_ADSPWDT			122
-#define TEGRA186_RESET_APE			123
-#define TEGRA186_RESET_DPAUX1			124
-#define TEGRA186_RESET_NVDEC			125
-#define TEGRA186_RESET_NVENC			126
-#define TEGRA186_RESET_NVJPG			127
-#define TEGRA186_RESET_PEX_USB_UPHY		128
-#define TEGRA186_RESET_QSPI			129
-#define TEGRA186_RESET_TSECB			130
-#define TEGRA186_RESET_VI_I2C			131
-#define TEGRA186_RESET_UARTE			132
-#define TEGRA186_RESET_TOP_GTE			133
-#define TEGRA186_RESET_SHSP			134
-#define TEGRA186_RESET_PEX_USB_UPHY_L5		135
-#define TEGRA186_RESET_PEX_USB_UPHY_L4		136
-#define TEGRA186_RESET_PEX_USB_UPHY_L3		137
-#define TEGRA186_RESET_PEX_USB_UPHY_L2		138
-#define TEGRA186_RESET_PEX_USB_UPHY_L1		139
-#define TEGRA186_RESET_PEX_USB_UPHY_L0		140
-#define TEGRA186_RESET_PEX_USB_UPHY_PLL1	141
-#define TEGRA186_RESET_PEX_USB_UPHY_PLL0	142
-#define TEGRA186_RESET_TSCTNVI			143
-#define TEGRA186_RESET_EXTPERIPH4		144
-#define TEGRA186_RESET_DSIPADCTL		145
-#define TEGRA186_RESET_AUD_MCLK			146
-#define TEGRA186_RESET_MPHY_CLK_CTL		147
-#define TEGRA186_RESET_MPHY_L1_RX		148
-#define TEGRA186_RESET_MPHY_L1_TX		149
-#define TEGRA186_RESET_UFSHC_LP			150
-#define TEGRA186_RESET_BPMP_NIC			151
-#define TEGRA186_RESET_BPMP_NSYSPORESET		152
-#define TEGRA186_RESET_BPMP_NRESET		153
-#define TEGRA186_RESET_BPMP_DBGRESETN		154
-#define TEGRA186_RESET_BPMP_PRESETDBGN		155
-#define TEGRA186_RESET_BPMP_PM			156
-#define TEGRA186_RESET_BPMP_CVC			157
-#define TEGRA186_RESET_BPMP_DMA			158
-#define TEGRA186_RESET_BPMP_HSP			159
-#define TEGRA186_RESET_TSCTNBPMP		160
-#define TEGRA186_RESET_BPMP_TKE			161
-#define TEGRA186_RESET_BPMP_GTE			162
-#define TEGRA186_RESET_BPMP_PM_ACTMON		163
-#define TEGRA186_RESET_AON_NIC			164
-#define TEGRA186_RESET_AON_NSYSPORESET		165
-#define TEGRA186_RESET_AON_NRESET		166
-#define TEGRA186_RESET_AON_DBGRESETN		167
-#define TEGRA186_RESET_AON_PRESETDBGN		168
-#define TEGRA186_RESET_AON_ACTMON		169
-#define TEGRA186_RESET_AOPM			170
-#define TEGRA186_RESET_AOVC			171
-#define TEGRA186_RESET_AON_DMA			172
-#define TEGRA186_RESET_AON_GPIO			173
-#define TEGRA186_RESET_AON_HSP			174
-#define TEGRA186_RESET_TSCTNAON			175
-#define TEGRA186_RESET_AON_TKE			176
-#define TEGRA186_RESET_AON_GTE			177
-#define TEGRA186_RESET_SCE_NIC			178
-#define TEGRA186_RESET_SCE_NSYSPORESET		179
-#define TEGRA186_RESET_SCE_NRESET		180
-#define TEGRA186_RESET_SCE_DBGRESETN		181
-#define TEGRA186_RESET_SCE_PRESETDBGN		182
-#define TEGRA186_RESET_SCE_ACTMON		183
-#define TEGRA186_RESET_SCE_PM			184
-#define TEGRA186_RESET_SCE_DMA			185
-#define TEGRA186_RESET_SCE_HSP			186
-#define TEGRA186_RESET_TSCTNSCE			187
-#define TEGRA186_RESET_SCE_TKE			188
-#define TEGRA186_RESET_SCE_GTE			189
-#define TEGRA186_RESET_SCE_CFG			190
-#define TEGRA186_RESET_ADSP_ALL			191
-/** @brief controls the power up/down sequence of UFSHC PSW partition. Controls LP_PWR_READY, LP_ISOL_EN, and LP_RESET_N signals */
-#define TEGRA186_RESET_UFSHC_LP_SEQ		192
-#define TEGRA186_RESET_SIZE			193
-
-#endif
diff --git a/include/dt-bindings/thermal/tegra124-soctherm.h b/include/dt-bindings/thermal/tegra124-soctherm.h
deleted file mode 100644
index 729ab9fc325e..000000000000
--- a/include/dt-bindings/thermal/tegra124-soctherm.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * This header provides constants for binding nvidia,tegra124-soctherm.
- */
-
-#ifndef _DT_BINDINGS_THERMAL_TEGRA124_SOCTHERM_H
-#define _DT_BINDINGS_THERMAL_TEGRA124_SOCTHERM_H
-
-#define TEGRA124_SOCTHERM_SENSOR_CPU 0
-#define TEGRA124_SOCTHERM_SENSOR_MEM 1
-#define TEGRA124_SOCTHERM_SENSOR_GPU 2
-#define TEGRA124_SOCTHERM_SENSOR_PLLX 3
-#define TEGRA124_SOCTHERM_SENSOR_NUM 4
-
-#endif
