| Message ID | 20240319-b4-qcom-livetree-v3-6-e1b38d9b4fa4@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Qualcomm platform USB support | expand |
On Tue, 19 Mar 2024 at 17:52, Caleb Connolly <caleb.connolly@linaro.org> wrote: > > Define the GDSC power domains for SDM845. > > Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> > Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> > --- > drivers/clk/qcom/clock-sdm845.c | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) > Reviewed-by: Sumit Garg <sumit.garg@linaro.org> -Sumit > diff --git a/drivers/clk/qcom/clock-sdm845.c b/drivers/clk/qcom/clock-sdm845.c > index ccb0cf245d33..b7154360894a 100644 > --- a/drivers/clk/qcom/clock-sdm845.c > +++ b/drivers/clk/qcom/clock-sdm845.c > @@ -145,13 +145,31 @@ static const struct qcom_reset_map sdm845_gcc_resets[] = { > [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 }, > [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, > }; > > +static const struct qcom_power_map sdm845_gdscs[] = { > + [PCIE_0_GDSC] = { 0x6b004 }, > + [PCIE_1_GDSC] = { 0x8d004 }, > + [UFS_CARD_GDSC] = { 0x75004 }, > + [UFS_PHY_GDSC] = { 0x77004 }, > + [USB30_PRIM_GDSC] = { 0xf004 }, > + [USB30_SEC_GDSC] = { 0x10004 }, > + [HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC] = { 0x7d030 }, > + [HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC] = { 0x7d03c }, > + [HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC] = { 0x7d034 }, > + [HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC] = { 0x7d038 }, > + [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = { 0x7d040 }, > + [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = { 0x7d048 }, > + [HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] = { 0x7d044 }, > +}; > + > static struct msm_clk_data sdm845_clk_data = { > .resets = sdm845_gcc_resets, > .num_resets = ARRAY_SIZE(sdm845_gcc_resets), > .clks = sdm845_clks, > .num_clks = ARRAY_SIZE(sdm845_clks), > + .power_domains = sdm845_gdscs, > + .num_power_domains = ARRAY_SIZE(sdm845_gdscs), > > .enable = sdm845_clk_enable, > .set_rate = sdm845_clk_set_rate, > }; > > -- > 2.44.0 >
diff --git a/drivers/clk/qcom/clock-sdm845.c b/drivers/clk/qcom/clock-sdm845.c index ccb0cf245d33..b7154360894a 100644 --- a/drivers/clk/qcom/clock-sdm845.c +++ b/drivers/clk/qcom/clock-sdm845.c @@ -145,13 +145,31 @@ static const struct qcom_reset_map sdm845_gcc_resets[] = { [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 }, [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, }; +static const struct qcom_power_map sdm845_gdscs[] = { + [PCIE_0_GDSC] = { 0x6b004 }, + [PCIE_1_GDSC] = { 0x8d004 }, + [UFS_CARD_GDSC] = { 0x75004 }, + [UFS_PHY_GDSC] = { 0x77004 }, + [USB30_PRIM_GDSC] = { 0xf004 }, + [USB30_SEC_GDSC] = { 0x10004 }, + [HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC] = { 0x7d030 }, + [HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC] = { 0x7d03c }, + [HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC] = { 0x7d034 }, + [HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC] = { 0x7d038 }, + [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = { 0x7d040 }, + [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = { 0x7d048 }, + [HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] = { 0x7d044 }, +}; + static struct msm_clk_data sdm845_clk_data = { .resets = sdm845_gcc_resets, .num_resets = ARRAY_SIZE(sdm845_gcc_resets), .clks = sdm845_clks, .num_clks = ARRAY_SIZE(sdm845_clks), + .power_domains = sdm845_gdscs, + .num_power_domains = ARRAY_SIZE(sdm845_gdscs), .enable = sdm845_clk_enable, .set_rate = sdm845_clk_set_rate, };