diff mbox series

[06/13] clk/qcom: sdm845: add USB clocks

Message ID 20240131-b4-qcom-livetree-v1-6-4071c0787db0@linaro.org
State New
Headers show
Series Qualcomm platform USB support | expand

Commit Message

Caleb Connolly Jan. 31, 2024, 3:16 p.m. UTC 
Most devices only initialise the USB clocks for us if we boot via
"fastboot boot", add the missing clock configuration to get both USB
ports working regardless of the bootloader state.

Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
---
 drivers/clk/qcom/clock-sdm845.c | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

Comments

Dan Carpenter Jan. 31, 2024, 3:38 p.m. UTC | #1 
On Wed, Jan 31, 2024 at 03:16:58PM +0000, Caleb Connolly wrote:
> @@ -121,6 +130,26 @@ static int sdm845_clk_enable(struct clk *clk)
>  
>  	debug("%s: clk %s\n", __func__, sdm845_clks[clk->id].name);
>  
> +	switch (clk->id) {
> +	case GCC_USB30_PRIM_MASTER_CLK:
> +		gdsc_enable(priv->base + USB30_PRIM_GDSCR);
> +		qcom_gate_clk_en(priv, GCC_USB_PHY_CFG_AHB2PHY_CLK);
> +		/* These numbers are just pulled from the frequency tables in the Linux driver */
> +		clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MASTER_CLK_CMD_RCGR,
> +				     (4.5 * 2) - 1, 0, 0, 1 << 8, 8);
> +		clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR,
> +				     1, 0, 0, 0, 8);
> +		clk_rcg_set_rate_mnd(priv->base, USB3_PRIM_PHY_AUX_CMD_RCGR,
> +				     1, 0, 0, 0, 8);
> +	case GCC_USB30_SEC_MASTER_CLK:

Is this supposed to break?  Otherwise can we add a "fallthrough;"
annotation?

> +		gdsc_enable(priv->base + USB30_SEC_GDSCR);
> +		qcom_gate_clk_en(priv, GCC_USB3_SEC_PHY_AUX_CLK);
> +
> +		qcom_gate_clk_en(priv, GCC_USB3_SEC_CLKREF_CLK);
> +		qcom_gate_clk_en(priv, GCC_USB3_SEC_PHY_COM_AUX_CLK);
> +		break;
> +	}

regards,
dan carpenter
diff mbox series

Patch

diff --git a/drivers/clk/qcom/clock-sdm845.c b/drivers/clk/qcom/clock-sdm845.c
index 5d6c0cdaeee5..e5033cacb216 100644
--- a/drivers/clk/qcom/clock-sdm845.c
+++ b/drivers/clk/qcom/clock-sdm845.c
@@ -21,6 +21,13 @@ 
 
 #define SE9_UART_APPS_CMD_RCGR	0x18148
 
+#define USB30_PRIM_MASTER_CLK_CMD_RCGR 0xf018
+#define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0xf030
+#define USB3_PRIM_PHY_AUX_CMD_RCGR 0xf05c
+
+#define USB30_PRIM_GDSCR 0xf004
+#define USB30_SEC_GDSCR 0x10004
+
 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
 	F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625),
 	F(14745600, CFG_CLK_SRC_GPLL0_EVEN, 1, 768, 15625),
@@ -57,6 +64,8 @@  static ulong sdm845_clk_set_rate(struct clk *clk, ulong rate)
 }
 
 static const struct gate_clk sdm845_clks[] = {
+	GATE_CLK(GCC_AGGRE_USB3_SEC_AXI_CLK,		0x82020, 0x00000001),
+	GATE_CLK(GCC_CFG_NOC_USB3_SEC_AXI_CLK,		0x05030, 0x00000001),
 	GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK,		0x5200c, 0x00000400),
 	GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK,		0x5200c, 0x00000800),
 	GATE_CLK(GCC_QUPV3_WRAP0_S2_CLK,		0x5200c, 0x00001000),
@@ -121,6 +130,26 @@  static int sdm845_clk_enable(struct clk *clk)
 
 	debug("%s: clk %s\n", __func__, sdm845_clks[clk->id].name);
 
+	switch (clk->id) {
+	case GCC_USB30_PRIM_MASTER_CLK:
+		gdsc_enable(priv->base + USB30_PRIM_GDSCR);
+		qcom_gate_clk_en(priv, GCC_USB_PHY_CFG_AHB2PHY_CLK);
+		/* These numbers are just pulled from the frequency tables in the Linux driver */
+		clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MASTER_CLK_CMD_RCGR,
+				     (4.5 * 2) - 1, 0, 0, 1 << 8, 8);
+		clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR,
+				     1, 0, 0, 0, 8);
+		clk_rcg_set_rate_mnd(priv->base, USB3_PRIM_PHY_AUX_CMD_RCGR,
+				     1, 0, 0, 0, 8);
+	case GCC_USB30_SEC_MASTER_CLK:
+		gdsc_enable(priv->base + USB30_SEC_GDSCR);
+		qcom_gate_clk_en(priv, GCC_USB3_SEC_PHY_AUX_CLK);
+
+		qcom_gate_clk_en(priv, GCC_USB3_SEC_CLKREF_CLK);
+		qcom_gate_clk_en(priv, GCC_USB3_SEC_PHY_COM_AUX_CLK);
+		break;
+	}
+
 	qcom_gate_clk_en(priv, clk->id);
 
 	return 0;