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([223.178.213.6]) by smtp.gmail.com with ESMTPSA id nr21-20020a17090b241500b0028b8b269aedsm1038997pjb.57.2023.12.17.23.24.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Dec 2023 23:24:51 -0800 (PST) From: Sumit Garg To: u-boot@lists.denx.de Cc: caleb.connolly@linaro.org, neil.armstrong@linaro.org, lukma@denx.de, seanga2@gmail.com, marex@denx.de, laetitia.mariottini@se.com, pascal.eberhard@se.com, abdou.saker@se.com, jimmy.lalande@se.com, benjamin.missey@non.se.com, daniel.thompson@linaro.org, Sumit Garg Subject: [PATCH 1/7] clk: apq8016: Add support for UART1 clocks Date: Mon, 18 Dec 2023 12:54:22 +0530 Message-Id: <20231218072428.1802969-2-sumit.garg@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231218072428.1802969-1-sumit.garg@linaro.org> References: <20231218072428.1802969-1-sumit.garg@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean SE HMIBSC board uses UART1 as the main debug console, so add corresponding clocks support. Signed-off-by: Sumit Garg --- drivers/clk/qcom/clock-apq8016.c | 44 ++++++++++++++++++++++++++++---- 1 file changed, 39 insertions(+), 5 deletions(-) diff --git a/drivers/clk/qcom/clock-apq8016.c b/drivers/clk/qcom/clock-apq8016.c index c0ce570edc7..fb663d2e92e 100644 --- a/drivers/clk/qcom/clock-apq8016.c +++ b/drivers/clk/qcom/clock-apq8016.c @@ -42,6 +42,14 @@ #define BLSP1_UART2_APPS_N (0x3040) #define BLSP1_UART2_APPS_D (0x3044) +#define BLSP1_UART1_BCR (0x2038) +#define BLSP1_UART1_APPS_CBCR (0x203C) +#define BLSP1_UART1_APPS_CMD_RCGR (0x2044) +#define BLSP1_UART1_APPS_CFG_RCGR (0x2048) +#define BLSP1_UART1_APPS_M (0x204C) +#define BLSP1_UART1_APPS_N (0x2050) +#define BLSP1_UART1_APPS_D (0x2054) + /* GPLL0 clock control registers */ #define GPLL0_STATUS_ACTIVE BIT(17) @@ -93,6 +101,33 @@ static int clk_init_sdc(struct msm_clk_priv *priv, int slot, uint rate) return rate; } +static const struct bcr_regs uart1_regs = { + .cfg_rcgr = BLSP1_UART1_APPS_CFG_RCGR, + .cmd_rcgr = BLSP1_UART1_APPS_CMD_RCGR, + .M = BLSP1_UART1_APPS_M, + .N = BLSP1_UART1_APPS_N, + .D = BLSP1_UART1_APPS_D, +}; + +/* UART: 115200 */ +static int clk_init_uart1(struct msm_clk_priv *priv) +{ + /* Enable AHB clock */ + clk_enable_vote_clk(priv->base, &gcc_blsp1_ahb_clk); + + /* 7372800 uart block clock @ GPLL0 */ + clk_rcg_set_rate_mnd(priv->base, &uart1_regs, 1, 144, 15625, + CFG_CLK_SRC_GPLL0, 16); + + /* Vote for gpll0 clock */ + clk_enable_gpll0(priv->base, &gpll0_vote_clk); + + /* Enable core clk */ + clk_enable_cbc(priv->base + BLSP1_UART1_APPS_CBCR); + + return 0; +} + static const struct bcr_regs uart2_regs = { .cfg_rcgr = BLSP1_UART2_APPS_CFG_RCGR, .cmd_rcgr = BLSP1_UART2_APPS_CMD_RCGR, @@ -102,7 +137,7 @@ static const struct bcr_regs uart2_regs = { }; /* UART: 115200 */ -static int clk_init_uart(struct msm_clk_priv *priv) +static int clk_init_uart2(struct msm_clk_priv *priv) { /* Enable AHB clock */ clk_enable_vote_clk(priv->base, &gcc_blsp1_ahb_clk); @@ -127,13 +162,12 @@ static ulong apq8016_clk_set_rate(struct clk *clk, ulong rate) switch (clk->id) { case 0: /* SDC1 */ return clk_init_sdc(priv, 0, rate); - break; case 1: /* SDC2 */ return clk_init_sdc(priv, 1, rate); - break; case 4: /* UART2 */ - return clk_init_uart(priv); - break; + return clk_init_uart2(priv); + case 5: /* UART1 */ + return clk_init_uart1(priv); default: return 0; }