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However, if some platforms require ICACHE or DCACHE to be disabled only for the smaller SPL stage, we should support such configurations in u-boot as well. Compile-tested for: - qemu arm64 - imx8 - stm32 and run-tested on: - Qualcomm RB3 platform Cc: Tom Rini Cc: Simon Glass Cc: Peng Fan Signed-off-by: Bhupesh Sharma Reviewed-by: Tom Rini --- arch/arm/Kconfig | 2 ++ arch/arm/cpu/armv8/Makefile | 4 ++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 36ee1e9a3c..92bff715e3 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -141,6 +141,7 @@ config THUMB2_KERNEL config SYS_ICACHE_OFF bool "Do not enable icache" + depends on !ARM64 help Do not enable instruction cache in U-Boot. @@ -153,6 +154,7 @@ config SPL_SYS_ICACHE_OFF config SYS_DCACHE_OFF bool "Do not enable dcache" + depends on !ARM64 help Do not enable data cache in U-Boot. diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile index bba4f570db..0d0c1728e4 100644 --- a/arch/arm/cpu/armv8/Makefile +++ b/arch/arm/cpu/armv8/Makefile @@ -5,13 +5,13 @@ extra-y := start.o +obj-y += cache_v8.o obj-y += cpu.o ifndef CONFIG_$(SPL_TPL_)TIMER obj-$(CONFIG_SYS_ARCH_TIMER) += generic_timer.o endif ifndef CONFIG_$(SPL_)SYS_DCACHE_OFF -obj-y += cache_v8.o -obj-y += cache.o +obj-y += cache.o endif ifdef CONFIG_SPL_BUILD obj-$(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) += exceptions.o